EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 279

• Manufacturer Part Number: EP4SGX360FH29C3N
• Description: IC STRATIX IV FPGA 360K 780HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX360FH29C3N

• Number Of Logic Elements/cells: 353600
• Number Of Labs/clbs: 14144
• Total Ram Bits: 22564
• Number Of I /o: 289
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

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SIV51008-3.2
Overview
Stratix IV Device Handbook Volume 1
February 2011
February 2011
SIV51008-3.2
This chapter describes the significant advantages of the high-speed differential I/O
interfaces and the dynamic phase aligner (DPA) over single-ended I/Os and their
contribution to the overall system bandwidth achievable with Stratix
references to Stratix IV devices in this chapter apply to Stratix IV E, GT, and GX
devices.
The Stratix IV device family consists of the Stratix IV E (Enhanced) devices without
high-speed clock data recovery (CDR) based transceivers, Stratix IV GT devices with
up to 48 CDR-based transceivers running up to 11.3 Gbps, and Stratix IV GX devices
with up to 48 CDR-based transceivers running up to 8.5 Gbps.
The following sections describe the Stratix IV high-speed differential I/O interfaces
and DPA:
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All Stratix IV E, GX, and GT devices have built-in serializer/deserializer (SERDES)
circuitry that supports high-speed LVDS interfaces at data rates of up to 1.6 Gbps.
SERDES circuitry is configurable to support source-synchronous communication
protocols such as Utopia, Rapid I/O, XSBI, small form factor interface (SFI), serial
peripheral interface (SPI), and asynchronous protocols such as SGMII and Gigabit
Ethernet.
The Stratix IV device family has the following dedicated circuitry for high-speed
differential I/O support:
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“Locations of the I/O Banks” on page 8–3
“LVDS Channels” on page 8–4
“LVDS SERDES” on page 8–8
“ALTLVDS Port List” on page 8–9
“Differential Transmitter” on page 8–11
“Differential Receiver” on page 8–17
“LVDS Interface with the Use External PLL Option Enabled” on page 8–26
“Left and Right PLLs (PLL_Lx and PLL_Rx)” on page 8–29
“Stratix IV Clocking” on page 8–30
“Source-Synchronous Timing Budget” on page 8–31
“Differential Pin Placement Guidelines” on page 8–38
Differential I/O buffer
Transmitter serializer
Receiver deserializer
8. High-Speed Differential I/O Interfaces
and DPA in Stratix IV Devices
®
IV FPGAs. All
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