EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 456

• Manufacturer Part Number: EP4SGX360FH29C3N
• Description: IC STRATIX IV FPGA 360K 780HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX360FH29C3N

• Number Of Logic Elements/cells: 353600
• Number Of Labs/clbs: 14144
• Total Ram Bits: 22564
• Number Of I /o: 289
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

1–12
Stratix IV Device Handbook Volume 2: Transceivers
Figure 1–7
EP4S100G2F40 Stratix IV GT devices.
Figure 1–7. Transceiver Channel, PLL, and PCIe Hard IP Block Locations in EP4S100G2F40
Stratix IV GT Devices
Notes to
(1) EP4S100G2F40ES1 devices do not have 10G ATX PLL blocks. Use the CMU PLL to generate transceiver clocks for
(2) If you are using the PCIe hard IP block, the EP4S100G2F40 device is not able to migrate to the EP4S100G5H40
channels configured at 11.3 Gbps.
device.
EP4S100G2F40
Figure
Transceiver Block QL2
Transceiver Block QL1
Transceiver Block QL0
shows the transceiver channel, PLL, and PCIe hard IP block locations in
10G Channel 3
10G Channel 2
10G Channel 1
10G Channel 0
CMU Channel 1
CMU Channel 0
10G Channel 1
10G Channel 0
10G Channel 3
10G Channel 2
CMU Channel 1
CMU Channel 0
10G Channel 1
10G Channel 0
10G Channel 3
10G Channel 2
ATX PLL (10G)
CMU Channel 1
CMU Channel 0
ATX PLL (6G)
1–7:
Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block QR2
Transceiver Block QR1
Transceiver Block QR0
February 2011 Altera Corporation
10G Channel 3
10G Channel 2
10G Channel 1
10G Channel 0
Transceiver Channel Locations
10G Channel 1
10G Channel 0
10G Channel 3
10G Channel 2
CMU Channel 1
CMU Channel 0
10G Channel 1
10G Channel 0
CMU Channel 1
CMU Channel 0
10G Channel 3
10G Channel 2
CMU Channel 1
CMU Channel 0
ATX PLL (10G)
ATX PLL (6G)