EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 581

• Manufacturer Part Number: EP4SGX360FH29C3N
• Description: IC STRATIX IV FPGA 360K 780HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX360FH29C3N

• Number Of Logic Elements/cells: 353600
• Number Of Labs/clbs: 14144
• Total Ram Bits: 22564
• Number Of I /o: 289
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
February 2011 Altera Corporation
The PCIe specification allows the PCIe interface to perform protocol functions; for
example, receiver detect, loopback, and beacon transmission, in specified power
states only. This requires the PHY-MAC layer to drive the tx_detectrxloopback and
tx_forceelecidle signals appropriately in each power state to perform these
functions.
tx_detectrxloopback and tx_forceelecidle signals in each power state.
Table 1–50. Logic Levels for tx_detectrxloopback and tx_forceelecidle in Different Power States
The PCIe specification requires the PHY to encode the receiver status on a 3-bit
RxStatus[2:0] signal. This status signal is used by the PHY-MAC layer for its
operation.
The PCIe interface block receives status signals from the transceiver channel PCS and
PMA blocks and encodes the status on the 3-bit output signal pipestatus[2:0] to the
FPGA fabric. The encoding of the status signals on pipestatus[2:0] is compliant
with the PCIe specification and is listed in
Table 1–51. Encoding of the Status Signals on pipestatus[2:0]
Two or more of the error conditions (for example, 8B/10B decode error [code group
violation], rate match FIFO overflow or underflow, and receiver disparity error), can
occur simultaneously. The PCIe interface follows the priority listed in
while encoding the receiver status on the pipestatus[2:0] port. For example, if the
PCIe interface receives an 8B/10B decode error and disparity error for the same
symbol, it drives 3'b100 on the pipestatus[2:0] signal.
pipestatus[2:0]
Power State
Receiver Status
3'b000
3'b001
3'b010
3'b011
3'b100
3'b101
3'b110
3'b111
P0s
P0
P1
P2
Table 1–50
0: normal mode
1: datapath in loopback mode
Don’t care
0: Electrical Idle
1: receiver detect
Don’t care
lists the logic levels that the PHY-MAC layer must drive on the
Elastic buffer (rate match FIFO) underflow
Elastic buffer (rate match FIFO) overflow
tx_detectrxloopback
One SKP symbol deleted
Received disparity error
One SKP symbol added
8B/10B decode error
Receiver detected
Received data OK
Description
Table
1–51.
Stratix IV Device Handbook Volume 2: Transceivers
0: Must be de-asserted
1: Illegal mode
0: Illegal mode
1: Must be asserted in this state
0: Illegal mode
1: Must be asserted in this state
De-asserted in this state for sending
beacon. Otherwise asserted.
tx_forceelecidle
Error Condition Priority
Table 1–51
N/A
N/A
5
6
1
2
3
4
1–137