EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 1032
EP4SGX360FH29C3N
Manufacturer Part Number
EP4SGX360FH29C3N
Description
IC STRATIX IV FPGA 360K 780HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
Specifications of EP4SGX360FH29C3N
Number Of Logic Elements/cells
353600
Number Of Labs/clbs
14144
Total Ram Bits
22564
Number Of I /o
289
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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2–14
Guidelines to Debug Transceiver-Based Designs
Stratix IV Device Handbook Volume 3
f
In the Compile to library option, select the corresponding library for the file selected.
Figure 2–2
the Stratix II GX device.
Figure 2–2. ModelSim Option to Compile Files in a Specific Library
Include all the libraries in the search path. Add the ALTGX and ALTGX_RECONFIG
MegaWizard Plug-In Manager-generated wrapper files (.v or .vhd) and all of the
design files to the library. Compile all the library files first, then the design files, and
lastly run the simulation.
For Verilog simulation, add the ALTGX and ALTGX_RECONFIG MegaWizard
Plug-In Manager-generated Verilog wrapper files (.v), the Altera library files, and all
of the design files. Compile all the library files first, then the simulation model file,
followed by the design files. Lastly, run the simulation.
These guidelines are further described in
Application”
For more information about functional register transfer level (RTL) simulation or
post-fit simulation, refer to the
Handbook.
This section provides guidelines to debug transceiver-based designs. If a system
failure occurs, the first step is to ensure the functionality of the logic within the FPGA.
Use the following information when you observe a system failure.
shows the ModelSim window compilation of files in a specific library for
below.
Simulation
Chapter 2: Transceiver Design Flow Guide for Stratix IV Devices
“Example 1: Fibre Channel Protocol
chapter in volume 3 of the Quartus II
Guidelines to Debug Transceiver-Based Designs
February 2011 Altera Corporation
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