EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 723

• Manufacturer Part Number: EP4SGX360FH29C3N
• Description: IC STRATIX IV FPGA 360K 780HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX360FH29C3N

• Number Of Logic Elements/cells: 353600
• Number Of Labs/clbs: 14144
• Total Ram Bits: 22564
• Number Of I /o: 289
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 2: Transceiver Clocking in Stratix IV Devices
FPGA Fabric-Transceiver Interface Clocking
FPGA Fabric-Transceiver Interface Clocking
Table 2–14. FPGA Fabric-Transceiver Interface Clocks
February 2011 Altera Corporation
pll_inclk
rx_cruclk
tx_clkout
coreclkout
rx_clkout
fixed_clk
Clock Name
1
CMU PLL input reference clock when
driven from an FPGA CLK input pin
Receiver CDR input reference clock when
driven from an FPGA CLK input pin
Phase compensation FIFO clock
Phase compensation FIFO clock
Phase compensation FIFO clock
PCIe receiver detect clock
The FPGA fabric-Transceiver interface clocks consist of clock signals from the FPGA
fabric to the transceiver blocks and clock signals from the transceiver blocks to the
FPGA fabric. These clock resources use the clock networks in the FPGA core that
include the global, regional, and periphery clock networks.
The FPGA fabric-Transceiver interface clocks can be subdivided into the following
three categories:
■
■
■
In Basic (PMA Direct) functional mode, only tx_clkout and rx_clkout are available
to clock the logic in the core. In bonded mode, you may use tx_clkout of one of the
channels to clock all of the channels. For receivers in bonded mode, you must use
separate rx_clkout for each channel.
Table 2–14
Input Reference Clocks—Refer to
Transceiver Datapath Interface Clocks—are used to transfer data, control, and
status signals between the FPGA fabric and the transceiver channels. The
transceiver channel forwards the tx_clkout signal (in non-bonded modes) or the
coreclkout signal (in bonded channel modes) to the FPGA fabric to clock the data
and control signals into the transmitter. The transceiver channel also forwards the
recovered rx_clkout clock (in configurations without rate matcher) or
tx_clkout/coreclkout (in configurations with rate matcher) to the FPGA fabric to
clock the data and status signals from the receiver into the FPGA fabric.
Other Transceiver Clocks—The following transceiver clocks form a part of the
FPGA fabric-Transceiver interface clocks:
■
■
■
cal_blk_clk—calibration block clock
fixed_clk—125 MHz fixed-rate clock used in the PCIe receiver detect circuitry
and for the adaptive equalization (AEQ) block
reconfig_clk—clock used for transceiver dynamic reconfiguration (for more
information, refer to
Clock Description
lists the FPGA fabric-Transceiver interface clocks.
Table 2–5 on page
(Note 1)
FPGA fabric-to-transceiver
FPGA fabric-to-transceiver
Transceiver-to-FPGA fabric
Transceiver-to-FPGA fabric
Transceiver-to-FPGA fabric
FPGA fabric-to-transceiver
(Part 1 of 2)
“Input Reference Clock Source” on page
Interface Direction
2–9)
Stratix IV Device Handbook Volume 2: Transceivers
Global clock
Global clock, Regional
clock
Global clock, Regional
clock, Periphery clock
Global clock, Regional
clock, Periphery clock
Global clock, Regional
clock, Periphery clock
Global clock, Regional
clock
Resource Utilization
FPGA Fabric Clock
2–3.
(1)
2–51