EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 129

EP4SGX360FH29C3N

Manufacturer Part Number

EP4SGX360FH29C3N

Description

IC STRATIX IV FPGA 360K 780HBGA

Manufacturer

Altera

Series

Stratix® IV GXr

Datasheets

1.EP4SGX110DF29C3N.pdf (80 pages)

2.EP4SGX110DF29C3N.pdf (1154 pages)

3.EP4SGX110DF29C3N.pdf (432 pages)

4.EP4SGX110DF29C3N.pdf (22 pages)

5.EP4SGX110DF29C3N.pdf (30 pages)

6.EP4SGX110DF29C3N.pdf (72 pages)

Specifications of EP4SGX360FH29C3N

Number Of Logic Elements/cells

353600

Number Of Labs/clbs

14144

Total Ram Bits

22564

Number Of I /o

289

Voltage - Supply

0.87 V ~ 0.93 V

Mounting Type

Surface Mount

Operating Temperature

0°C ~ 85°C

Package / Case

780-HBGA

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Number Of Gates

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BOSTOCK HK LIMITED

Part Number:

EP4SGX360FH29C3N

Manufacturer:

ALTERA

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Chapter 5: Clock Networks and PLLs in Stratix IV Devices

Clock Networks in Stratix IV Devices

February 2011 Altera Corporation

Clock Output Connections

Dedicated clock pins can drive PLLs over dedicated routing; they do not require the

global or regional network. Compensated inputs, which are a subset of dedicated

clock pins, drive PLLs that can only compensate the input delay when a dedicated

clock pin is in the same I/O bank as the PLL used.

PLLs in Stratix IV devices can drive up to 20 RCLK networks and four GCLK

networks. For Stratix IV PLL connectivity to GCLK networks, refer to

Quartus II software automatically assigns PLL clock outputs to RCLK and GCLK

networks.

Table 5–5

Table 5–5. Stratix IV PLL Connectivity to the GCLK Networks

Table 5–6

Table 5–6. Stratix IV RCLK Outputs From the PLL Clock Outputs

GCLK0

GCLK1

GCLK2

GCLK3

GCLK4

GCLK5

GCLK6

GCLK7

GCLK8

GCLK9

GCLK10

GCLK11

GCLK12

GCLK13

GCLK14

GCLK15

Note to

(1) Only PLL counter outputs C0 - C3 can drive the GCLK networks.

RCLK[0..11]

RCLK[12..31]

RCLK[32..43]

RCLK[44..63]

Clock Resource

Clock Network

Table

lists how the PLL clock outputs connect to the GCLK networks.

lists how the PLL clock outputs connect to the RCLK networks.

5–5:

—

PLL Number

—

(Note 1)

Stratix IV Device Handbook Volume 1

—

(Part 1 of 2)

—

Table

—

5–5. The

—

5–13

—

EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 129

EP4SGX360FH29C3N

Specifications of EP4SGX360FH29C3N

Available stocks

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