EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 716

• Manufacturer Part Number: EP4SGX360FH29C3N
• Description: IC STRATIX IV FPGA 360K 780HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX360FH29C3N

• Number Of Logic Elements/cells: 353600
• Number Of Labs/clbs: 14144
• Total Ram Bits: 22564
• Number Of I /o: 289
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

2–44
Figure 2–25. Receiver Datapath Clocking in x4 Bonded Channel Configuration with Deskew FIFO
Note to
(1) The red lines represent the FPGA fabric-Transceiver interface clock, the green lines represent the low-speed parallel clock, the dark red lines
Stratix IV Device Handbook Volume 2: Transceivers
represent the Ch0 parallel recovered clock, and the blue lines represent the serial recovered clock.
Figure
2–25:
rx_coreclk[2]
rx_coreclk[1]
rx_coreclk[0]
rx_coreclk[3]
FPGA
Fabric
FPGA Fabric-Transceiver
Interface Clock
XAUI functional mode has ×4 bonded channel configuration with deskew FIFO.
Figure 2–25
configurations with deskew FIFO.
In ×4 bonded channel configurations with deskew FIFO, the CDR in each receiver
channel recovers the serial clock from the received data. The serial recovered clock is
divided within each channel’s receiver PMA to generate the parallel recovered clock.
The deserializer uses the serial recovered clock in the receiver PMA. The parallel
recovered clock and deserialized data is forwarded to the receiver PCS in each
channel.
coreclkout
x4 Bonded Channel Configuration with Deskew FIFO
hard IP
hard IP
hard IP
hard IP
PCIe
PCIe
PCIe
PCIe
/2
Reference
Reference
Clock
Clock
Input
Input
shows the receiver datapath clocking in ×4 channel bonding
Interface
Interface
Interface
Interface
PIPE
PIPE
PIPE
PIPE
Compensation
Compensation
Compensation
Compensation
RX Phase
RX Phase
RX Phase
RX Phase
CMU1 PLL
FIFO
FIFO
CMU0 PLL
FIFO
FIFO
Ordering
Ordering
Ordering
Ordering
Byte
Byte
Byte
Byte
Divider
CMU1
Clock
Divider
Serializer
Serializer
CMU0
Serializer
Clock
Serializer
Byte
/2
Byte
/2
Byte
/2
De-
De-
Byte
De-
De-
/2
Low-Speed Parallel Clock from CMU0 Clock Divider
Low-Speed Parallel Clock from CMU0 Clock Divider
Low-Speed Parallel Clock from CMU0 Clock Divider
Low-Speed Parallel Clock from CMU0 Clock Divider
CMU0 Channel
CMU1 Channel
Decoder
Decoder
Decoder
8B/10B
8B/10B
8B/10B
Decoder
8B/10B
Match
Match
Rate
FIFO
Match
FIFO
Match
Rate
Rate
FIFO
Low-Speed Parallel Clock
Rate
FIFO
Recovered Clock
Recovered Clock
Recovered Clock
Ch0 Parallel
Ch0 Parallel
Receiver Channel PCS
Ch0 Parallel
Receiver Channel PCS
Receiver Channel PCS
Receiver Channel PCS
Chapter 2: Transceiver Clocking in Stratix IV Devices
Deskew
Deskew
Deskew
Deskew
FIFO
FIFO
FIFO
FIFO
Aligner
Aligner
Aligner
Aligner
Word
Word
Word
Word
Channel 3
Channel 2
Channel 1
Channel 0
Receiver Channel PMA
Receiver Channel PMA
Serializer
Receiver Channel PMA
Serializer
Serializer
Serializer
Receiver Channel PMA
Recovered Clock
Recovered Clock
Recovered Clock
De-
De-
De-
De-
Transceiver Channel Datapath Clocking
Recovered Clock
Ch3 Parallel
Ch2 Parallel
Ch0 Parallel
Ch1 Parallel
February 2011 Altera Corporation
CDR
CDR
CDR
CDR
Serial Recovered Clock
Serial Recovered Clock
Serial Recovered Clock
Serial Recovered Clock
Input Reference Clock
Input Reference Clock
Input Reference Clock
Input Reference Clock
(Note 1)