EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 732

• Manufacturer Part Number: EP4SGX360FH29C3N
• Description: IC STRATIX IV FPGA 360K 780HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX360FH29C3N

• Number Of Logic Elements/cells: 353600
• Number Of Labs/clbs: 14144
• Total Ram Bits: 22564
• Number Of I /o: 289
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

2–60
Table 2–15. Transmitter Phase Compensation FIFO Read Clocks
Stratix IV Device Handbook Volume 2: Transceivers
Non-Bonded Channel
Configuration
×4 Bonded Channel
Configuration
×8 Bonded Channel
Configuration
Configuration
1
1
1
Table 2–15
Quartus II software selects in various configurations.
To ensure that you understand the 0 PPM clock driver rule, the Quartus II software
expects the following set of user assignments whenever you use the tx_coreclk port
to drive the transmitter phase compensation FIFO write clock:
■
Failing to make this assignment correctly when using the tx_coreclk port results in a
Quartus II compilation error.
The GXB 0 PPM core clock setting allows the following clock drivers to drive the
tx_coreclk ports:
■
■
■
■
■
The Quartus II software does not allow gated clocks or clocks generated in FPGA
logic to drive the tx_coreclk ports.
Because the GXB 0 PPM core clock setting allows the FPGA CLK input pins and
transceiver refclk pins as the clock driver, the Quartus II compiler cannot determine
if there is a 0 PPM difference between the FIFO write clock and read clock for each
channel.
You must ensure that the clock driver for all connected tx_coreclk ports has a 0 PPM
difference with respect to the FIFO read clock in those channels.
Parallel transmitter PCS clock from the local
clock divider in the associated channel
(tx_clkout)
Low-speed parallel clock from the CMU0
clock divider of the associated transceiver
block (coreclkout)
Low-speed parallel clock from the CMU0
clock divider of the master transceiver block
(coreclkout from master transceiver block)
GXB 0 PPM Core Clock Setting
tx_clkout in non-bonded channel configurations
coreclkout in bonded channel configurations
FPGA_CLK input pins
Transceiver refclk pins
Clock output from left and right and top and bottom PLLs (PLL_L, PLL_R, and
PLL_T, PLL_B)
Without Byte Serializer
lists the transmitter phase compensation FIFO read clocks that the
Transmitter Phase Compensation FIFO Read Clock
Divide-by-two version of the parallel transmitter PCS
clock from the local clock divider in the associated
channel (tx_clkout)
Divide-by-two version of the low-speed parallel
clock from the CMU0 clock divider of the associated
transceiver block (coreclkout)
Divide-by-two version of the low-speed parallel
clock from the CMU0 clock divider of the master
transceiver block (coreclkout from master
transceiver block)
Chapter 2: Transceiver Clocking in Stratix IV Devices
With Byte Serializer
FPGA Fabric-Transceiver Interface Clocking
February 2011 Altera Corporation