EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 745

• Manufacturer Part Number: EP4SGX360FH29C3N
• Description: IC STRATIX IV FPGA 360K 780HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX360FH29C3N

• Number Of Logic Elements/cells: 353600
• Number Of Labs/clbs: 14144
• Total Ram Bits: 22564
• Number Of I /o: 289
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 2: Transceiver Clocking in Stratix IV Devices
Configuration Examples
Configuration Examples
February 2011 Altera Corporation
To use this feature, you must create an ALTGX instance with a single channel in
Transmitter Only mode that uses the required CMU PLL or ATX PLL. To create the
ALTGX instance, follow these steps:
1. Choose Basic (PMA Direct) ×N mode as the protocol.
2. Select Transmitter Only operation mode.
3. Select the input clock frequency.
4. Select the appropriate values of data rate and channel width based on the desired
Equation 2–1.
5. You can select the PLL bandwidth by choosing Tx PLL bandwidth mode.
6. You can instantiate the pll_locked port to indicate the PLL lock status.
7. You can instantiate pll_powerdown or gxb_powerdown to enable the PLL PFD power
8. Use tx_clkout of the ALTGX instance as the clock source for clocking user logic in
This section describes the following examples:
■
■
■
■
output clock frequency. To generate a 250 MHz clock using an input clock
frequency of 50 MHz, select a channel width of 10 and a data rate of 2500 Mbps
(Equation
down control.
the FPGA fabric.
“Configuration Example 1: Configuring 24 Channels in Basic (PMA Direct) ×N
Mode in the EP4S100G5F45 Device” on page 2–74
“Configuration Example 2: Configuring Sixteen Identical Channels Across Four
Transceiver Blocks” on page 2–76
“Configuration Example 3: Configuring Sixteen Channels Across Four Transceiver
Blocks” on page 2–77
“Configuration Example 4: Configuring Left and Right, Left, or Right PLL in VCO
Bypass Mode” on page 2–79
2–1).
f
out
=
channel width
data rate
Stratix IV Device Handbook Volume 2: Transceivers
2–73