EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 136
EP4SGX360FH29C3N
Manufacturer Part Number
EP4SGX360FH29C3N
Description
IC STRATIX IV FPGA 360K 780HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
Specifications of EP4SGX360FH29C3N
Number Of Logic Elements/cells
353600
Number Of Labs/clbs
14144
Total Ram Bits
22564
Number Of I /o
289
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4SGX360FH29C3N
Manufacturer:
Bussmann
Quantity:
40 000
Company:
Part Number:
EP4SGX360FH29C3N
Manufacturer:
ALTERA21
Quantity:
53
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5–20
Table 5–7. PLL Availability for Stratix IV Devices (Part 2 of 2)
Table 5–8. PLL Features in Stratix IV Devices (Part 1 of 2)
Stratix IV Device Handbook Volume 1
EP4SE820
EP4SGX70
EP4SGX110
EP4SGX180
EP4SGX230
EP4SGX290
EP4SGX360
EP4SGX530
C (output) counters
M, N, C counter sizes
Dedicated clock outputs
Clock input pins
External feedback input pin
Spread-spectrum input clock tracking
Device
Package
H1152
H1517
F1760
F1152
F1152
F1152
F1932
F1152
F1517
F1760
F1932
H1152
H1517
F1760
F1932
Feature
F1517
F1152
F1517
F1152
F1517
F1760
H780
H780
F780
F780
F780
F780
(2)
All Stratix IV PLLs have the same core analog structure with only minor differences in
the features that are supported.
left/right PLLs in Stratix IV devices.
v
v
v
v
v
v
v
v
L1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
v
v
v
v
v
v
v
v
v
v
v
v
v
L2
v
v
v
v
v
v
—
v
v
—
v
v
v
v
4 single-ended or 4 differential pin pairs
6 single-ended or 4 single-ended and 1
L3
v
v
v
—
—
—
—
v
v
v
v
v
—
—
v
v
v
—
v
v
v
—
—
—
—
—
—
Stratix IV Top/Bottom PLLs
Single-ended or differential
v
v
v
v
v
v
v
v
L4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
differential pair
1 to 512
Yes
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
T1
Table 5–8
10
(Note 1)
(3)
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
T2
—
—
—
—
—
—
lists the features of top/bottom and
Chapter 5: Clock Networks and PLLs in Stratix IV Devices
B1
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
B2
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
—
—
—
—
—
—
v
v
2 single-ended or 1 differential pair
4 single-ended or 4 differential pin
Stratix IV Left/Right PLLs
R1
v
v
v
v
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
v
v
—
—
v
v
February 2011 Altera Corporation
—
—
Single-ended only
1 to 512
Yes
pairs
PLLs in Stratix IV Devices
R2
v
v
v
—
v
v
v
v
v
v
v
v
v
v
—
v
v
v
v
v
v
v
v
—
—
—
—
7
(3)
R3
v
v
v
v
v
v
v
v
v
v
v
v
v
v
—
—
—
—
—
—
—
—
—
—
—
—
—
R4
v
v
v
v
v
v
v
v
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
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