EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 725

• Manufacturer Part Number: EP4SGX360FH29C3N
• Description: IC STRATIX IV FPGA 360K 780HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX360FH29C3N

• Number Of Logic Elements/cells: 353600
• Number Of Labs/clbs: 14144
• Total Ram Bits: 22564
• Number Of I /o: 289
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 2: Transceiver Clocking in Stratix IV Devices
FPGA Fabric-Transceiver Interface Clocking
February 2011 Altera Corporation
1
Example 3 assumes channels 0 and 1, driven by CMU0_PLL in a transceiver block, are
identical. Also, channels 2 and 3, driven by CMU1_PLL in the same transceiver block,
are identical. In this case, the Quartus II software automatically drives the write port
of the transmitter phase compensation FIFO in channels 0 and 1 with the
tx_clkout[0] signal. It also drives the write port of the transmitter phase
compensation FIFO in channels 2 and 3 with the tx_clkout[2] signal. Use the
tx_clkout[0] signal to clock the transmitter data and control logic for channels 0
and 1 in the FPGA fabric. Use the tx_clkout[2] signal to clock the transmitter data
and control logic for channels 2 and 3 in the FPGA fabric.
This configuration uses two FPGA global and/or regional clock resources, one for the
tx_clkout[0] signal and the other for the tx_clkout[2] signal.
Example 3: Two Groups of Two Identical Channels in a Transceiver Block
Stratix IV Device Handbook Volume 2: Transceivers
2–53