EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 788
EP4SGX360FH29C3N
Manufacturer Part Number
EP4SGX360FH29C3N
Description
IC STRATIX IV FPGA 360K 780HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
Specifications of EP4SGX360FH29C3N
Number Of Logic Elements/cells
353600
Number Of Labs/clbs
14144
Total Ram Bits
22564
Number Of I /o
289
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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EP4SGX360FH29C3N
Manufacturer:
Bussmann
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EP4SGX360FH29C3N
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ALTERA21
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3–34
Figure 3–18. The ×N_Top and ×N_Bottom Clock Line Connections
Stratix IV Device Handbook Volume 2: Transceivers
Figure 3–18
Transceiver Block GXBR1
Transceiver Block GXBR2
Transceiver Block GXBR0
ATX R1 PLL Block
CMU0 Channel
ATX R0 PLL Block
CMU1 Channel
CMU0 Channel
CMU1 Channel
CMU1 Channel
CMU0 Channel
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
shows the different drivers of the ×N_Top and ×N_Bottom clock lines.
CMU1 GXBR0
CMU1 GXBR2
CMU1 GXBR1
x1
x1
x1
CMU0 GXBR2
CMU0 GXBR1
CMU0 GXBR0
Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices
x1
x1
x1
x4_GXBR2
Combining Transceiver Channels in Basic (PMA Direct) Configurations
x4_GXBR0
x4_GXBR1
xN_Bottom
xN_Top
February 2011 Altera Corporation
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