EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 900

• Manufacturer Part Number: EP4SGX360FH29C3N
• Description: IC STRATIX IV FPGA 360K 780HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX360FH29C3N

• Number Of Logic Elements/cells: 353600
• Number Of Labs/clbs: 14144
• Total Ram Bits: 22564
• Number Of I /o: 289
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

5–54
Figure 5–26. CMU PLLs in a Transceiver Block in CMU PLL Reconfiguration Mode
Note to
(1) Depending on the mode you select, PCS may or may not be present.
Stratix IV Device Handbook Volume 2: Transceivers
Figure
refclk0
refclk1
5–26:
1
The dynamic reconfiguration controller powers down only the selected CMU PLL.
The other CMU PLL is not affected.
Blocks Reconfigured in CMU PLL Reconfiguration Mode
Each transceiver block has two CMU PLLs—CMU0 PLL and CMU1 PLL.You can
reconfigure each of these CMU PLLs to a different data rate in this mode.
shows a view of the reconfigurable blocks using CMU PLL reconfiguration mode.
ALTGX MegaWizard Plug-In Manager Setup for CMU PLL Reconfiguration Mode
If you want to reconfigure the CMU PLL to another data rate, enable .mif generation
and set up the ALTGX MegaWizard Plug-In Manager, as described in the following
steps. The dynamic reconfiguration controller reconfigures the CMU PLL with the
new information stored in the .mif.
1. Select the Channel and Transmitter PLL reconfiguration option in the Modes
2. Provide the new data rate you want the CMU PLL to run at in the General screen.
The logical reference index of CMU0 PLL within a transceiver block is always the
complement of the logical reference index of CMU1 PLL.
screen.
clock
mux
clock
mux
CMU Channels
CMU0 PLL
CMU1 PLL
Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Logical
TX PLL
select
clock
mux
Full Duplex Transceiver Channel
Dynamic Reconfiguration Modes Implementation
LOCAL
DIVIDER
TX CHANNEL
RX CHANNEL
RX CDR
February 2011 Altera Corporation
TX PMA + TX PCS
RX PMA + RX PCS
(1)
Figure 5–26