EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 910

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EP4SGX360FH29C3N

Manufacturer Part Number
EP4SGX360FH29C3N
Description
IC STRATIX IV FPGA 360K 780HBGA
Manufacturer
Altera
Series
Stratix® IV GXr

Specifications of EP4SGX360FH29C3N

Number Of Logic Elements/cells
353600
Number Of Labs/clbs
14144
Total Ram Bits
22564
Number Of I /o
289
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

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0
5–64
Figure 5–33. Write Transaction in Data Rate Division in Transmitter Mode
Note to
(1) For this example, you want to reconfigure the local divider settings of the transmitter channel to Divide by 4. Therefore, the value set at
Stratix IV Device Handbook Volume 2: Transceivers
rate_switch_ctrl[1:0] is 2'b10.
logical_channel_address
reconfig_mode_sel[2:0]
rate_switch_ctrl[1:0] (1)
Figure
5–33:
reconfig_clk
write_all
busy
For this example, the value set in the What is the number of channels controlled by
the reconfig controller? option of the ALTGX_RECONFIG MegaWizard Plug-In
Manager is 4. Therefore, the logical_channel_address input is 2 bits wide. Also, you
must reconfigure the local divider settings of the transmitter channel whose logical
channel address is 2'b01.
transmitter mode.
3'bXXX
2'bXX
2'bXX
Figure 5–33
shows a write transaction in data rate division in
3'b011
2'b10
2'b01
Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Modes Implementation
February 2011 Altera Corporation
2'bXX
2'bXX

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