EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 148
EP4SGX360FH29C3N
Manufacturer Part Number
EP4SGX360FH29C3N
Description
IC STRATIX IV FPGA 360K 780HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
Specifications of EP4SGX360FH29C3N
Number Of Logic Elements/cells
353600
Number Of Labs/clbs
14144
Total Ram Bits
22564
Number Of I /o
289
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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5–32
Figure 5–29. External Feedback Mode in Stratix IV Devices
Stratix IV Device Handbook Volume 1
Clock Multiplication and Division
inclk
Figure 5–28
clocks in external feedback mode.
Figure 5–28. Phase Relationship Between the PLL Clocks in External Feedback Mode
Note to
(1) The PLL clock outputs can lead or lag the fbin clock input.
Figure 5–29
Each Stratix IV PLL provides clock synthesis for PLL output ports using
M/(N* post-scale counter) scaling factors. The input clock is divided by a pre-scale
factor, n, and is then multiplied by the m feedback factor. The control loop drives the
VCO to match f
divides down the high-frequency VCO. For multiple PLL outputs with different
frequencies, the VCO is set to the least common multiple of the output frequencies
that meets its frequency specifications. For example, if the output frequencies required
from one PLL are 33 and 66 MHz, the Quartus II software sets the VCO to 660 MHz
(the least common multiple of 33 and 66 MHz within the VCO range). Then the
post-scale counters scale down the VCO frequency for each output port.
÷n
Figure
5–28:
shows an example waveform of the phase relationship between the PLL
shows external feedback mode implementation in Stratix IV devices.
fbin Clock Input Pin
Clock Outputs (1)
in
PFD
Dedicated PLL
PLL Reference
(M/N). Each output port has a unique post-scale counter that
Clock Port (1)
PLL Clock at
Clock at the
the Register
Input Pin
CP/LF
Phase Aligned
VCO
÷C0
÷C1
÷m
Chapter 5: Clock Networks and PLLs in Stratix IV Devices
fbout
fbin
PLL_<#>_CLKOUT#
PLL_<#>_CLKOUT#
February 2011 Altera Corporation
external
board
trace
PLLs in Stratix IV Devices
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