EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 61

• Manufacturer Part Number: EP4SGX360FH29C3N
• Description: IC STRATIX IV FPGA 360K 780HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX360FH29C3N

• Number Of Logic Elements/cells: 353600
• Number Of Labs/clbs: 14144
• Total Ram Bits: 22564
• Number Of I /o: 289
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices
Overview
February 2011 Altera Corporation
Address Clock Enable Support
All Stratix IV memory blocks support address clock enable, which holds the previous
address value for as long as the signal is enabled (addressstall = 1). When the
memory blocks are configured in dual-port mode, each port has its own independent
address clock enable. The default value for the address clock enable signals is low
(disabled).
Figure 3–2
referred to by the port name addressstall.
Figure 3–2. Address Clock Enable
Figure 3–3
Figure 3–3. Address Clock Enable During Read Cycle Waveform
latched address
(inside memory)
addressstall
q (asynch)
rdaddress
q (synch)
shows an address clock enable block diagram. The address clock enable is
shows the address clock enable waveform during the read cycle.
inclock
rden
doutn-1
doutn
addressstall
an
address[0]
address[N]
a0
clock
doutn
a0
dout0
a1
1
0
dout0
1
0
a2
address[0]
address[N]
register
register
a1
dout1
a3
dout1
address[0]
address[N]
Stratix IV Device Handbook Volume 1
a4
a4
dout4
a5
dout4
a5
dout5
a6
3–5