EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 769

• Manufacturer Part Number: EP4SGX360FH29C3N
• Description: IC STRATIX IV FPGA 360K 780HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX360FH29C3N

• Number Of Logic Elements/cells: 353600
• Number Of Labs/clbs: 14144
• Total Ram Bits: 22564
• Number Of I /o: 289
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices
Combining Transceiver Instances in Multiple Transceiver Blocks
February 2011 Altera Corporation
Figure 3–6
Figure 3–6. Combined Transceiver Instances After Compilation for Example 4
You can force the placement of the transceiver channels in specific transceiver banks
by assigning pins to the tx_dataout and rx_datain ports of inst0 and inst1.
Even though inst0 instantiates seven transceiver channels, the ALTGX MegaWizard
Plug-In Manager provides only a one-bit wide pll_inclk port for inst0. In your
design, provide only one clock input for the pll_inclk port. The Quartus II software
uses two transceiver blocks to fit the seven channels and internally connects the input
reference clock (connected to the pll_inclk port in your design) to the CMU PLLs of
two transceiver blocks.
shows the transceiver instances after compilation.
Effective Data Rate: 4.25 Gbps
Effective Data Rate: 4.25 Gbps
Ch5 of inst0
Ch4 of inst0
Ch0 of inst1
Effective Data Rate: 4.25 Gbps
Ch6 of inst0
Effective Data Rate: 4.25 Gbps
Ch1 of inst0
Effective Data Rate: 4.25 Gbps
Ch0 of inst0
Effective Data Rate: 4.25 Gbps
Effective Data Rate: 4.25 Gbps
Ch3 of inst0
Ch2 of inst0
Effective Data Rate: 4.25 Gbps
Transceiver Block 1
Transceiver Block 0
Base Data Rate:
Base Data Rate:
4.25 Gbps
CMU PLL
CMU PLL
4.25 Gbps
Stratix IV Device Handbook Volume 2: Transceivers
3–15