EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 795
EP4SGX360FH29C3N
Manufacturer Part Number
EP4SGX360FH29C3N
Description
IC STRATIX IV FPGA 360K 780HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
Specifications of EP4SGX360FH29C3N
Number Of Logic Elements/cells
353600
Number Of Labs/clbs
14144
Total Ram Bits
22564
Number Of I /o
289
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices
Combining Transceiver Channels in Basic (PMA Direct) Configurations
February 2011 Altera Corporation
You can also combine channels configured in Basic (PMA Direct) ×N mode with
bonded ×4 and ×8 functional modes. For example scenarios, refer to
page 3–19
Consider the unsupported placement design example shown
placement is unsupported because of the ×N_Top clock line contention between the
ATX PLL and the CMU0 PLL in transceiver block 0.
Figure 3–22. Unsupported Placement Due to ×N Clock Line Contention for Example 11
Note to
(1) The red lines represent the ×N top clock line and the blue lines represent the ×4 clock line.
Example 11
Figure
and
3–22:
Figure 3–10 on page
CMU0
PLL
CMU0 Channel
Inst0:Channel 0
Inst0:Channel 1
Inst0:Channel 2
Inst0:Channel 3
Inst0:Channel 4
Inst0:Channel 5
Inst0:Channel 6
Inst0:Channel 7
Inst0:Channel 8
Inst0:Channel 9
Inst1:Channel 0
RX
RX
RX
RX
RX
RX
RX
RX
RX
RX
RX
Inst0:Channel 1
Inst0:Channel 1
ATX PLL R1
GXBR1
(5 Gbps)
GXBR0
Central
TX
TX
TX
TX
TX
Divider
TX
TX
TX
TX
TX
TX
Clock
3–22.
using the clock
Contention in
This channel cannot get its clock from the
line
ATX PLL due to clock contention
x4 Clock Line (1)
Stratix IV Device Handbook Volume 2: Transceivers
xN Top Clock Line (1)
Figure
Figure 3–8 on
3–22. The
3–41
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