EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 589

• Manufacturer Part Number: EP4SGX360FH29C3N
• Description: IC STRATIX IV FPGA 360K 780HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX360FH29C3N

• Number Of Logic Elements/cells: 353600
• Number Of Labs/clbs: 14144
• Total Ram Bits: 22564
• Number Of I /o: 289
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Figure 1–115. Low-Speed Parallel Clock Switching in PCIe ×1 Mode
February 2011 Altera Corporation
Low-Speed Parallel Clock
pipephydonestatus
1
rateswitch
The PCIe clock switch circuitry in the local clock divider block performs the clock
switch between 250 MHz and 500 MHz on the low-speed parallel clock when
switching between Gen1 (2.5 Gbps) and Gen2 (5 Gbps) signaling rates. It indicates
successful completion of clock switch on the pcie_gen2switchdone signal to the PCIe
rateswitch controller. The PCIe rateswitch controller forwards the clock switch
completion status to the PCIe interface block. The PCIe interface block communicates
the clock switch completion status to the PHY-MAC layer by asserting the
pipephydonestatus signal for one parallel clock cycle.
Figure 1–115
Gen2 (500 MHz) in response to the change in the logic level on the rateswitch signal.
The rateswitch completion is shown marked with a one clock cycle assertion of the
pipephydonestatus signal.
Time T1 from a transition on the rateswitch signal to the assertion of
pipephydonestatus is pending characterization.
As a result of the signaling rateswitch between Gen1 (2.5 Gbps) and Gen2 (5 Gbps),
the FPGA fabric-transceiver interface clock switches between 125 MHz and 250 MHz.
The FPGA fabric-transceiver interface clock clocks the read side and write side of the
transmitter phase compensation FIFO and the receiver phase compensation FIFO,
respectively. It is also routed to the FPGA fabric on a global or regional clock resource
and looped back to clock the write port and read port of the transmitter phase
compensation FIFO and the receiver phase compensation FIFO, respectively. Due to
the routing delay between the write and read clock of the transmitter and receiver
phase compensation FIFOs, the write pointers and read pointers might collide during
a rateswitch between 125 MHz and 250 MHz. To avoid collision of the phase
compensation FIFO pointers, the PCIe rateswitch controller automatically disables
and resets the pointers during clock switch. When the PCIe clock switch circuitry in
the local clock divider indicates successful clock switch completion, the PCIe
rateswitch controller releases the phase compensation FIFO pointer resets.
250 MHz (Gen1)
shows the low-speed parallel clock switch between Gen1 (250 MHz) and
T1
500 MHz (Gen2)
Stratix IV Device Handbook Volume 2: Transceivers
T1
250 MHz (Gen1)
1–145