EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 816

• Manufacturer Part Number: EP4SGX360FH29C3N
• Description: IC STRATIX IV FPGA 360K 780HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX360FH29C3N

• Number Of Logic Elements/cells: 353600
• Number Of Labs/clbs: 14144
• Total Ram Bits: 22564
• Number Of I /o: 289
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

4–10
Figure 4–5. Sample Reset Sequence for Four Receiver and Transmitter Channels—Receiver CDR in Manual Lock Mode
Notes to
(1) For t
(2) For t
(3) For t
Stratix IV Device Handbook Volume 2: Transceivers
Output Status Signals
CDR Control Signals
Figure
pll_powerdown
LTR_LTD_Manual
LTD_Manual
rx_locktorefclk[0]
rx_locktorefclk[3]
rx_locktodata[0]
rx_locktodata[3]
Reset Signals
rx_pll_locked[0]
pll _ powerdown
rx _analogreset
rx_pll_locked[3]
tx _digitalreset
rx _digitalreset
4–5:
duration, refer to the
pll _ locked
duration, refer to the
duration, refer to the
busy
Receiver and Transmitter Channel—Receiver CDR in Manual Lock Mode
This configuration contains both a transmitter and receiver channel. For XAUI
functional mode, with the receiver CDR in manual lock mode, use the reset sequence
shown in
1
t
pll_powerdown (1)
DC and Switching Characteristics for Stratix IV Devices
Figure
DC and Switching Characteristics for Stratix IV Devices
DC and Switching Characteristics for Stratix IV Devices
2
4–5.
4
3
Minimum of Two Parallel Clock Cycles
5
6
7
7
t
Chapter 4: Reset Control and Power Down in Stratix IV Devices
LTR_LTD_Manual (2)
t
LTD_Manual (3)
8
8
8
8
chapter.
chapter.
chapter.
9
February 2011 Altera Corporation
Transceiver Reset Sequences