EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 37

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EP4SGX360FH29C3N

Manufacturer Part Number
EP4SGX360FH29C3N
Description
IC STRATIX IV FPGA 360K 780HBGA
Manufacturer
Altera
Series
Stratix® IV GXr

Specifications of EP4SGX360FH29C3N

Number Of Logic Elements/cells
353600
Number Of Labs/clbs
14144
Total Ram Bits
22564
Number Of I /o
289
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

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© 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off.
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www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but
reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any
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specifications before relying on any published information and before placing orders for products or services.
SIV51002-3.1
Logic Array Blocks
Stratix IV Device Handbook Volume 1
February 2011
February 2011
SIV51002-3.1
This chapter describes the features of the logic array blocks (LABs) in the Stratix
core fabric. LABs are made up of adaptive logic modules (ALMs) that you can
configure to implement logic functions, arithmetic functions, and register functions.
LABs and ALMs are the basic building blocks of the Stratix IV device. Use these to
configure logic, arithmetic, and register functions. The ALM provides advanced
features with efficient logic usage and is completely backward-compatible.
This chapter contains the following sections:
Each LAB consists of ten ALMs, various carry chains, shared arithmetic chains, LAB
control signals, local interconnect, and register chain connection lines. The local
interconnect transfers signals between ALMs in the same LAB. The direct link
interconnect allows the LAB to drive into the local interconnect of its left and right
neighbors. Register chain connections transfer the output of the ALM register to the
adjacent ALM register in the LAB. The Quartus
the LAB or adjacent LABs, allowing the use of local, shared arithmetic chain, and
register chain connections for performance and area efficiency.
“Logic Array Blocks”
“Adaptive Logic Modules” on page 2–5
2. Logic Array Blocks and Adaptive Logic
Modules in Stratix IV Devices
®
II Compiler places associated logic in
®
Subscribe
IV

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