EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 881

• Manufacturer Part Number: EP4SGX360FH29C3N
• Description: IC STRATIX IV FPGA 360K 780HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX360FH29C3N

• Number Of Logic Elements/cells: 353600
• Number Of Labs/clbs: 14144
• Total Ram Bits: 22564
• Number Of I /o: 289
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Modes Implementation
Figure 5–20. Option 2 for Receiver Core Clocking (Channel and CMU PLL Reconfiguration Mode)
February 2011 Altera Corporation
tx_clkout[0]
tx_clkout[1]
tx_clkout[2]
FPGA Fabric
Figure 5–20
channels of a transceiver block.
■
■
Consider the following scenario:
■
■
■
Option 3 is applicable in this scenario.
High-speed serial clock generated by the CMU0 PLL
High-speed serial clock generated by the CMU1 PLL
Low-speed parallel clock generated by the local divider of the transceiver
Enable this option if you want the individual channel’s rx_clkout signal to
provide the read clock to its respective Receive Phase Compensation FIFO.
This option is typically enabled when the channel is reconfigured from a Basic or
Protocol configuration with or without rate matching to another Basic or Protocol
configuration with or without rate matching.
TX1/RX1: GIGE configuration to SONET/SDH OC48 configuration.
TX2/RX2: Basic 2.5 Gbps configuration with rate matching disabled to Basic
1.244 Gbps configuration with rate matching disabled.
Channel and CMU PLL reconfiguration mode is enabled in the
ALTGX_RECONFIG MegaWizard Plug-In Manager.
Option 3: Use the Respective Channel Receiver Core Clocks
shows the respective tx_clkout of each channel clocking the respective
TX0 (2 Gbps/1 Gbps)
TX1 (4 Gbps/1 Gbps)
TX2 (3.125 Gbps/1 Gbps)
Transceiver Block
TX3 (2 Gbps)
RX0
RX2
RX3
RX1
Stratix IV Device Handbook Volume 2: Transceivers
CMU1 PLL
CMU0 PLL
5–35