EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 934

• Manufacturer Part Number: EP4SGX360FH29C3N
• Description: IC STRATIX IV FPGA 360K 780HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX360FH29C3N

• Number Of Logic Elements/cells: 353600
• Number Of Labs/clbs: 14144
• Total Ram Bits: 22564
• Number Of I /o: 289
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

5–88
Table 5–16. Dynamic Reconfiguration Controller Port List (ALTGX_RECONFIG Instance) (Part 13 of 13)
Error Indication During Dynamic Reconfiguration
Stratix IV Device Handbook Volume 2: Transceivers
ctrl_waitrequest
Notes to
(1) Not all combinations of the input bits are legal values.
(2) In PCIe mode, this input must be tied to 001 to be PCIe-compliant.
(3) For the various dynamic reconfiguration controller input and output ports and the software settings, refer to the
(4) For the various transceiver input and output ports and the software settings, refer to the
Megafunction User Guide for Stratix IV Devices
chapter.
Table
5–16:
Port Name
The ALTGX_RECONFIG MegaWizard Plug-In Manager provides an error status
signal when you select the Enable illegal mode checking option or the Enable self
recovery option in the Error checks/data rate switch screen. The conditions under
which the error signal is asserted are:
■
Enable illegal mode checking option—When you select this option, the dynamic
reconfiguration controller checks whether an attempted operation falls under one
of the conditions listed below. The dynamic reconfiguration controller detects
these conditions within two reconfig_clk cycles, de-asserts the busy signal, and
asserts the error signal for two reconfig_clk cycles.
■
■
■
■
PMA controls, read operation—None of the output ports (rx_eqctrl_out,
rx_eqdcgain_out, tx_vodctrl_out, tx_preemp_0t_out, tx_preemp_1t_out, and
tx_preemp_2t_out) are selected in the ALTGX_RECONFIG instance and the
read signal is asserted.
PMA controls, write operation—None of the input ports (rx_eqctrl,
rx_eqdcgain, tx_vodctrl, tx_preemp_0t, tx_preemp_1t, and tx_preemp_2t) are
selected in the ALTGX_RECONFIG instance and the write_all signal is
asserted.
TX Data Rate Switch using Local Divider-read operation option—The read
transaction is valid only for data rate division in transmitter mode
TX Data Rate Switch using Local Divider-write operation with unsupported
value option:
■
■
■
The rate_switch_ctrl input port is set to 11
The reconfig_mode_sel input port is set to 3 (if other reconfiguration mode
options are selected in the Reconfiguration settings screen)
The write_all signal is asserted
Output
Output
chapter.
Input/
Used for EyeQ control. If asserted, this port indicates that the EyeQ
controller is busy with a read or write operation. You must wait
until this signal goes low before you perform the next operation.
Ensure that the values on the ctrl_read, ctrl_write,
ctrl_readdata, and ctrl_writedata ports are constant when
ctrl_waitrequest is asserted.
Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
ALTGX Transceiver Setup Guide for Stratix IV Devices
Error Indication During Dynamic Reconfiguration
Description
February 2011 Altera Corporation
ALTGX_RECONFIG
(Note
3),
(4)