EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 751

• Manufacturer Part Number: EP4SGX360FH29C3N
• Description: IC STRATIX IV FPGA 360K 780HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX360FH29C3N

• Number Of Logic Elements/cells: 353600
• Number Of Labs/clbs: 14144
• Total Ram Bits: 22564
• Number Of I /o: 289
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 2: Transceiver Clocking in Stratix IV Devices
Configuration Examples
Table 2–20. Quartus II Assignments for Appendix Example 4
February 2011 Altera Corporation
From
To
Assignment Name
Value
Note to
(1) This is an example design hierarchy path for the rx_clkout[9] signal.
Table
Configuration Example 4: Configuring Left and Right, Left, or Right PLL in
VCO Bypass Mode
2–20:
1
Table 2–20
scheme shown in
This example relates to
page
To configure the left and right, left, or right PLL in VCO bypass mode, follow these
steps:
1. Under the General/Modes tab, enter the desired input reference clock frequency.
Figure 2–41. No Compensation Option Used for Configuration Example 4
top_level/top_xcvr_instance1/altgx_component/rx_clkout[9]
rx_datain[15..0]
GXB 0 PPM Core Clock Setting
ON
a. Under PLL Type, select Left_Right_PLL.
b. Under Operation mode, select the With no compensation option
2–17.
(Figure
lists the Quartus II assignments that you must make for the clocking
2–41).
Figure
“Left and Right, Left, or Right PLL in VCO Bypass Mode” on
2–40.
Stratix IV Device Handbook Volume 2: Transceivers
(1)
2–79