EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 637

• Manufacturer Part Number: EP4SGX360FH29C3N
• Description: IC STRATIX IV FPGA 360K 780HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX360FH29C3N

• Number Of Logic Elements/cells: 353600
• Number Of Labs/clbs: 14144
• Total Ram Bits: 22564
• Number Of I /o: 289
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Figure 1–157. Reverse Serial Loopback Datapath (Grayed-Out Blocks are Not Active in this Mode)
February 2011 Altera Corporation
Fabric
FPGA
RX Phase
Compen-
sation
FIFO
Reverse Serial Loopback
Reverse serial loopback is available as a subprotocol under Basic functional mode. In
reverse serial loopback mode, the data is received through the rx_datain port,
retimed through the receiver CDR and sent out to the tx_dataout port. The received
data is also available to the FPGA logic. No dynamic pin control is available to select
or deselect reverse serial loopback.
datapath for reverse serial loopback mode.
The active block of the transmitter channel is only the transmitter buffer. You can
change the output differential voltage and the pre-emphasis first post tap values on
the transmitter buffer through the ALTGX MegaWizard Plug-In Manager or through
the dynamic reconfiguration controller. Reverse serial loopback is often implemented
when using a bit error rate tester (BERT) on the upstream transmitter.
TX Phase
Compen-
Ordering
sation
FIFO
Byte
Serialzier
De-Serializer
Byte
Byte
Encoder
8B/10B
8B/10B
Decoder
Figure 1–157
Transmitter Channel PCS
Receiver Channel PCS
shows the transceiver channel
Aligner
Stratix IV Device Handbook Volume 2: Transceivers
Word
Loopback
Reverse
Serializer
Serial
Transmitter Channel PMA
Receiver Channel PMA
De-
Serializer
Receiver
CDR
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