EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 147

• Manufacturer Part Number: EP4SGX360FH29C3N
• Description: IC STRATIX IV FPGA 360K 780HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX360FH29C3N

• Number Of Logic Elements/cells: 353600
• Number Of Labs/clbs: 14144
• Total Ram Bits: 22564
• Number Of I /o: 289
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 5: Clock Networks and PLLs in Stratix IV Devices
PLLs in Stratix IV Devices
Figure 5–26. ZDB Mode in Stratix IV PLLs
Note to
(1) The bidirectional I/O pin must be assigned to the PLL_<#>_FB_CLKOUT0p pin for left and right PLLs and to the PLL_<#>_FBp_/CLKOUT1 pin for
February 2011 Altera Corporation
top and bottom PLLs.
Figure
5–26:
1
inclk
When using ZDB mode, to avoid signal reflection, do not place board traces on the
bi-directional I/O pin.
Figure 5–27
ZDB mode.
Figure 5–27. Phase Relationship Between the PLL Clocks in ZDB Mode
Note to
(1) The internal PLL clock output can lead or lag the external PLL clock outputs.
External Feedback Mode
In external feedback mode, the external feedback input pin (fbin) is phase-aligned
with the clock input pin, as shown in
remove clock delay and skew between devices. This mode is supported on all
Stratix IV PLLs.
In external feedback mode, the output of the M counter (FBOUT) feeds back to the PLL
fbin input (using a trace on the board) becoming part of the feedback loop. Also, use
one of the dual-purpose external clock outputs as the fbin input pin in this mode.
When using external feedback mode, you must use the same I/O standard on the
input clock, feedback input, and output clocks. Left and right PLLs support this mode
when using single-ended I/O standards only.
÷n
Figure
5–27:
shows an example waveform of the PLL clocks’ phase relationship in
PLL Clock at the
Register Clock Port (1)
PFD
Dedicated PLL
Clock Outputs
PLL Reference
Clock at the
Input Pin
CP/LF
Phase Aligned
VCO
Figure
÷C0
÷C1
÷m
5–28. Aligning these clocks allows you to
fbout
fbin
PLL_<#>_CLKOUT#
PLL_<#>_CLKOUT#
Stratix IV Device Handbook Volume 1
bidirectional
I/O pin (1)
5–31