EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 781
EP4SGX360FH29C3N
Manufacturer Part Number
EP4SGX360FH29C3N
Description
IC STRATIX IV FPGA 360K 780HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
Specifications of EP4SGX360FH29C3N
Number Of Logic Elements/cells
353600
Number Of Labs/clbs
14144
Total Ram Bits
22564
Number Of I /o
289
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices
Combining Transceiver Channels in Basic (PMA Direct) Configurations
February 2011 Altera Corporation
Example 5
Consider a design example configuration with a Basic (PMA Direct) ×1 instance with
the number of channels set to 7 in the ALTGX MegaWizard Plug-In Manager. With
this setting, the ALTGX MegaWizard Plug-In Manager provides 7 bits of
gxb_powerdown, rx_analogreset, and pll_powerdown ports.
In this case, the Quartus II software attempts to combine the five channels in the
instance to one transceiver block and the remaining two channels to the second
transceiver block, assuming that the gxb_powerdown and pll_powerdown ports for the
five channels are driven from the same logic.
conditions before and after compilation.
Figure 3–12. Logical View of the Instance with Seven Channels Before Compilation for
Example 5
Receiver and Transmitter configuration:
Basic (PMA Direct) x1 mode
Number of channels = 7
Inst0
Figure 3–12
Stratix IV Device Handbook Volume 2: Transceivers
and
CMU PLL
Figure 3–13
show the
3–27
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