EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 879

• Manufacturer Part Number: EP4SGX360FH29C3N
• Description: IC STRATIX IV FPGA 360K 780HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX360FH29C3N

• Number Of Logic Elements/cells: 353600
• Number Of Labs/clbs: 14144
• Total Ram Bits: 22564
• Number Of I /o: 289
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Modes Implementation
Figure 5–19. Option 1 for Receiver Core Clocking (Channel and CMU PLL Reconfiguration Mode)
February 2011 Altera Corporation
tx_clkout[0]
FPGA Fabric
Low-speed parallel clock generated by the TX0 local divider (tx_clkout[0])
High-speed serial clock generated by the CMU0 PLL
High-speed serial clock generated by the CMU1 PLL
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■
Consider the following scenario:
■
■
■
Option 1 is applicable in this scenario.
Figure 5–19
transceiver block.
Enable this option if you want tx_clkout of the first channel (channel 0) of the
transceiver block to provide the read clock to the Receive Phase Compensation
FIFOs of the remaining receiver channels in the transceiver block.
This option is typically enabled when all the channels of a transceiver block are in
a Basic or Protocol configuration with rate matching enabled and are reconfigured
to another Basic or Protocol configuration with rate matching enabled.
Four regular transceiver channels configured to the Basic 2 Gbps functional mode
with rate matching enabled.
Channel and CMU PLL reconfiguration mode is enabled in the
ALTGX_RECONFIG MegaWizard Plug-In Manager.
You want to reconfigure all four regular transceiver channels to 3.125 Gbps
configuration with rate matching enabled.
Option 1: Share a Single Transmitter Core Clock Between Receivers
shows the sharing of channel 0’s tx_clkout between all four channels of a
Transceiver Block
TX3 (2 Gbps)
TX1 (2 Gbps)
TX2 (2 Gbps)
TX0 (2 Gbps)
RX3
RX0
RX1
RX2
Stratix IV Device Handbook Volume 2: Transceivers
switch to 3.125 Gbps with Rate Matching
Four regular transceiver channels
Rate Matching and set up to
configured at Basic 2G with
CMU1 PLL
CMU0 PLL
5–33