EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 1037

• Manufacturer Part Number: EP4SGX360FH29C3N
• Description: IC STRATIX IV FPGA 360K 780HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX360FH29C3N

• Number Of Logic Elements/cells: 353600
• Number Of Labs/clbs: 14144
• Total Ram Bits: 22564
• Number Of I /o: 289
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 2: Transceiver Design Flow Guide for Stratix IV Devices
Example 1: Fibre Channel Protocol Application
Table 2–5. Multiple Channels
Table 2–6. Configuring Clocking (Part 1 of 2)
February 2011 Altera Corporation
Does the Stratix IV GX transceiver support these two
configurations and allow you to combine them within the
same transceiver block
Is there support for two different input reference clocks?
Do the refclk pins support the required frequency
range?
f
f
f
The design requires a Transmitter and Receiver configuration for two channels and a
Transmitter Only configuration for one channel
Dynamic Reconfiguration
If your application requires you to dynamically reconfigure the transceiver PMA
controls, ensure that you understand the settings, options, and user logic required to
enable this feature.
For more information, refer to the “Interfacing ALTGX and ALTGX_RECONFIG
Instances” section in the
For more information about initiating read and write transactions, refer to the
“Dynamically Reconfiguring PMA Controls” section in the
Stratix IV Devices
If you are using the channel reconfiguration feature, enable the appropriate options in
the ALTGX and ALTGX_RECONFIG MegaWizard Plug-In Managers.
You can dynamically use the reconfiguration modes to reconfigure different
functional blocks in a transceiver channel using .mifs. For information about
generating .mifs, refer to the “Channel and CMU PLL Reconfiguration Mode Details”
section in the
Clocking
Consider the questions listed in
Questions
Questions
Dynamic Reconfiguration in Stratix IV Devices
chapter.
Dynamic Reconfiguration in Stratix IV Devices
Yes
The available FPGA fabric interface width is 20 or 40 bits to
support 4.25 Gbps and 1.0625 Gbps data rates, respectively.
This FPGA fabric interface facilitates 8B/10B encoding and
decoding in the FPGA fabric without additional
re-arrangement of the received parallel data to a 10-bit
boundary.
Yes
The Stratix IV GX transceiver has two refclk pins for each
transceiver block.
Yes
The minimum frequency range of refclk is 50 MHz; the
maximum frequency range is 622.08 MHz.
Table 2–6
before configuring clocking.
(Table
Answer
Answer
2–5).
chapter.
Stratix IV Device Handbook Volume 3
Dynamic Reconfiguration in
chapter.
2–19