EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 577

• Manufacturer Part Number: EP4SGX360FH29C3N
• Description: IC STRATIX IV FPGA 360K 780HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX360FH29C3N

• Number Of Logic Elements/cells: 353600
• Number Of Labs/clbs: 14144
• Total Ram Bits: 22564
• Number Of I /o: 289
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Figure 1–108. Transmitter Buffer Electrical Idle State
February 2011 Altera Corporation
1
1
tx_forcelecidle
tx_dataout
The minimum period of time for which the tx_forceelecidle signal must be asserted
high such that the transmitter buffer stays in electrical idle state for at least 20 ns is
pending characterization.
The PCIe specification requires the transmitter buffer to be in electrical idle in certain
power states. For more information about the tx_forceelecidle signal levels
required in different PCIe power states, refer to
During the detect substate of the link training and status state machine (LTSSM), the
PCIe protocol requires the transmitter channel to perform a receiver detect sequence
to detect if a receiver is present at the far end of each lane. The PCIe specification
requires the receiver detect operation to be performed during the P1 power state.
The PCIe interface block in Stratix IV GX and GT transceivers provide an input signal
tx_detectrxloopback for the receiver detect operation. When the input signal
tx_detectrxloopback is asserted high in the P1 power state, the PCIe interface block
sends a command signal to the transmitter buffer in that channel to initiate a receiver
detect sequence. In the P1 power state, the transmitter buffer must always be in the
electrical idle state. After receiving this command signal, the receiver detect circuitry
creates a step voltage at the output of the transmitter buffer. If an active receiver (that
complies with the PCIe input impedance requirements) is present at the far end, the
time constant of the step voltage on the trace is higher when compared with the time
constant of the step voltage when the receiver is not present. The receiver detect
circuitry monitors the time constant of the step signal seen on the trace to determine if
a receiver was detected. The receiver detect circuitry monitor requires a 125-MHz
clock for operation that you must drive on the fixedclk port.
For the receiver detect circuitry to function reliably, the AC-coupling capacitor on the
serial link and the receiver termination values used in your system must be compliant
to the PCIe Base Specification 2.0.
Receiver detect circuitry communicates the status of the receiver detect operation to
the PCIe interface block. If a far-end receiver is successfully detected, the PCIe
interface block asserts pipephydonestatus for one clock cycle and synchronously
drives the pipestatus[2:0] signal to 3'b011. If a far-end receiver is not detected, the
PCIe interface block asserts pipephydonestatus for one clock cycle and synchronously
drives the pipestatus[2:0] signal to 3'b000.
Receiver Detection
T1
>20 ns
Table 1–50 on page
Stratix IV Device Handbook Volume 2: Transceivers
1–137.
1–133