EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 747
EP4SGX360FH29C3N
Manufacturer Part Number
EP4SGX360FH29C3N
Description
IC STRATIX IV FPGA 360K 780HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
Specifications of EP4SGX360FH29C3N
Number Of Logic Elements/cells
353600
Number Of Labs/clbs
14144
Total Ram Bits
22564
Number Of I /o
289
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Part Number:
EP4SGX360FH29C3N
Manufacturer:
Bussmann
Quantity:
40 000
Company:
Part Number:
EP4SGX360FH29C3N
Manufacturer:
ALTERA21
Quantity:
53
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Chapter 2: Transceiver Clocking in Stratix IV Devices
Configuration Examples
February 2011 Altera Corporation
Figure 2–38. Twenty-Four Channels on the Right Side of the EP4S100G5F45 Device Configured in
Basic (PMA Direct) ×N Mode for Configuration Example 1
Note to
(1) The green line represents the PLL cascade clock line and the blue lines represent the 6G ATX PLL block.
Figure
2–38:
(Transmitter Data
Generation Logic)
(Transmitter Data
Generation Logic)
FPGA Fabric
FPGA Fabric
FPGA CLK Pin
Dedicated
meet interface timing)
(VCO Bypass Mode)
(Phase Shift 315º to
PLL_R1
PLL_R2
PLL Cascade
Clock Line
Reference
tx_clkout
Clock
Transceiver Block GXBR3
Transceiver Block GXBR2
Transceiver Block GXBR0
Transceiver Block GXBR1
ATX PLL R2 (10G)
ATX PLL R1 (6G)
ATX PLL R0 (6G)
CMU1 Channel
CMU0 Channel
CMU1 Channel
CMU0 Channel
CMU1 Channel
CMU0 Channel
CMU1 Channel
CMU0 Channel
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
Stratix IV Device Handbook Volume 2: Transceivers
(Note 1)
xN_Bottom
xN_Top
2–75
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