EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 472

• Manufacturer Part Number: EP4SGX360FH29C3N
• Description: IC STRATIX IV FPGA 360K 780HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX360FH29C3N

• Number Of Logic Elements/cells: 353600
• Number Of Labs/clbs: 14144
• Total Ram Bits: 22564
• Number Of I /o: 289
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

1–28
Stratix IV Device Handbook Volume 2: Transceivers
Table 1–11
Table 1–11. tx_forcedisp and tx_dispval Port Values
Figure 1–24
mode by forcing a positive disparity K28.5 when it was supposed to be a negative
disparity K28.5. In this example, a series of K28.5 code groups are continuously being
sent. The stream alternates between a positive running disparity (RD+) K28.5 and a
negative running disparity (RD-) K28.5 to maintain a neutral overall disparity. The
current running disparity at time n + 3 indicates that the K28.5 in time n + 4 should be
encoded with a negative disparity. Because tx_forcedisp is high at time n + 4, and
tx_dispval is low, the K28.5 at time n + 4 is encoded as a positive disparity code
group.
Figure 1–24. 8B/10B Encoder Force Running Disparity Operation in Single-Width Mode
Figure 1–25
mode by forcing a positive disparity on a negative disparity K28.5. In this example, a
series of K28.5 are continuously being sent. The stream alternates between a positive
ending running disparity (RD+) K28.5 and a negative ending running disparity (RD-)
K28.5 as governed by the 8B/10B encoder specification to maintain a neutral overall
disparity. The current running disparity at the end of time n + 2 indicates that the
K28.5 at the low byte position in time n + 4 should be encoded with a positive
disparity. Because tx_forcedisp is high at time n + 4, the low signal level of
tx_dispval is used to convert the lower byte K28.5 to be encoded as a positive
disparity code word. As the upper bit of tx_forcedisp is low at n + 4, the high byte
K28.5 takes the current running disparity from the low byte.
tx_forcedisp
Current Running
Disparity
tx_ctrlenable
tx_forcedisp
dataout[9:0]
0
1
1
tx_dispval
lists the tx_forcedisp and tx_dispval port values.
tx_in[7:0]
shows the current running disparity being altered in Basic single-width
shows the current running disparity being altered in Basic double-width
clock
17C
BC
RD-
n
tx_dispval
X
0
1
n + 1
283
RD+
BC
n + 2
17C
BC
RD-
Current running disparity has no change
Encoded data has positive disparity
Encoded data has negative disparity
Chapter 1: Transceiver Architecture in Stratix IV Devices
n + 3
RD+
283
BC
n + 4
283
BC
RD+
Disparity Value
n + 5
17C
RD-
BC
February 2011 Altera Corporation
Transceiver Block Architecture
n + 6
RD+
283
BC
n + 7
RD-
17C
BC