EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 502

• Manufacturer Part Number: EP4SGX360FH29C3N
• Description: IC STRATIX IV FPGA 360K 780HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX360FH29C3N

• Number Of Logic Elements/cells: 353600
• Number Of Labs/clbs: 14144
• Total Ram Bits: 22564
• Number Of I /o: 289
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

1–58
Figure 1–47. Deserializer Operation in Single-Width Mode
Stratix IV Device Handbook Volume 2: Transceivers
f
After offset cancellation is complete, the divider settings are restored. Then the
reconfiguration block sends and receives data to the ALTGX instance using the
reconfig_togxb and reconfig_fromgxb buses. Connect the buses between the
ALTGX_RECONFIG and ALTGX instances. The de-assertion of the busy signal from
the offset cancellation control logic indicates the offset cancellation process is
complete.
Due to the offset cancellation process, the transceiver reset sequence has changed. For
more information about the offset cancellation process, refer to the
Power Down in Stratix IV Devices
Deserializer
The deserializer block clocks in serial input data from the receiver buffer using the
high-speed serial recovered clock and deserializes it using the low-speed parallel
recovered clock. It forwards the deserialized data to the receiver PCS channel.
In single-width mode, the deserializer supports 8-bit and 10-bit deserialization
factors. In double-width mode, the deserializer supports 16-bit and 20-bit
deserialization factors.
Figure 1–47
deserialization factor.
Received Data
Recovery
Clock
Unit
High-Speed Serial Recovered Clock
Low-Speed Parallel Recovered Clock
shows the deserializer operation in single-width mode with a 10-bit
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D1
D0
chapter.
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D3
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D1
D0
Chapter 1: Transceiver Architecture in Stratix IV Devices
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To Word
Aligner
February 2011 Altera Corporation
Transceiver Block Architecture
Reset Control and