EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 756

• Manufacturer Part Number: EP4SGX360FH29C3N
• Description: IC STRATIX IV FPGA 360K 780HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX360FH29C3N

• Number Of Logic Elements/cells: 353600
• Number Of Labs/clbs: 14144
• Total Ram Bits: 22564
• Number Of I /o: 289
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

3–2
Glossary of Terms
Table 3–1. Glossary of Terms Used in this Chapter
Stratix IV Device Handbook Volume 2: Transceivers
Regular Channels
Basic (PMA Direct)
Non-Basic (PMA
Direct)
Basic (PMA Direct) ×1
Basic (PMA Direct) ×N
Configuration
f
■
■
■
Each transmitter channel has a local divider (/1, /2, or /4) that divides the high clock
output of the CMU PLL to provide high-speed serial and low-speed parallel clocks for
its physical coding sublayer (PCS) and physical medium attachment (PMA)
functional blocks.
You can configure the RX CDR present in the receiver channel to a distinct data rate
and provide separate input reference clocks. Each receiver channel also contains a
local divider that divides the high-speed clock output of the RX CDR and provides
clocks for its PCS and PMA functional blocks. To enable transceiver channel settings,
the Quartus
interface. The ALTGX MegaWizard Plug-In Manager allows you to instantiate a single
transceiver channel or multiple transceiver channels in Receiver and Transmitter,
Receiver only, and Transmitter only configurations.
Table 3–1
For more information about transceiver channel set up using a Basic (PMA Direct) ×N
configuration, refer to the
This refers to the Basic (PMA Direct) configuration that you can use for both regular and CMU
channels. Basic (PMA Direct) mode has two variations, ×1 and ×N. The term “Basic (PMA Direct)”
used in this chapter refers to both ×1 and ×N and to regular/CMU Channels. Any specific reference
to ×1 and ×N or regular/CMU channels is stated explicitly.
This term refers to all single channel non-bonded configurations (for example, GIGE, PCI Express
[PCIe] ×1) or bonded channel configurations that have PCS enabled (for example, Basic ×4 and ×8,
XAUI, PCIe ×4 and ×8). Also, any reference to a channel in non-Basic (PMA Direct) mode indicates
that the channel is a regular transceiver channel.
A transceiver channel set up in this configuration uses the high-speed serial clock from the CMU
PLL that is present within the same transceiver block. You can select this configuration by setting
the Which protocol you will be using? option to Basic (PMA Direct) and the Which sub protocol
This refers to the four transceiver channels in each transceiver block that contain PCS.
you will be using? option to none.
A transceiver channel set up in this configuration uses the ×N high-speed clock lines. You can
select this configuration by setting the Which protocol you will be using? option to Basic (PMA
direct) and the Which sub protocol you will be using? option to ×N.
“Combining Transceiver Channels When You Enable the Adaptive Equalization
(AEQ) Feature” on page 3–47
“Combination Requirements for Stratix IV Devices” on page 3–49
“Summary” on page 3–49
lists the terms used in the chapter.
®
II software provides the ALTGX MegaWizard
Transceiver Clocking in Stratix IV Devices
Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices
Description
TM
February 2011 Altera Corporation
Plug-In Manager
chapter.
Glossary of Terms
®