EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 678
EP4SGX360FH29C3N
Manufacturer Part Number
EP4SGX360FH29C3N
Description
IC STRATIX IV FPGA 360K 780HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
Specifications of EP4SGX360FH29C3N
Number Of Logic Elements/cells
353600
Number Of Labs/clbs
14144
Total Ram Bits
22564
Number Of I /o
289
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Part Number:
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Manufacturer:
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Part Number:
EP4SGX360FH29C3N
Manufacturer:
ALTERA21
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2–6
Figure 2–4. Input Reference Clock Sources Across Transceiver Blocks for Stratix IV GT Devices
Stratix IV Device Handbook Volume 2: Transceivers
To FPGA Fabric
Figure 2–4
receiver CDRs in four transceiver blocks on the right side of the EP4S100G5F45
device. In this figure, the input reference clock sources for four transceiver blocks are
located only on the right side of the EP4S100G5F45 device but the device has similar
input reference clock resources available for the four transceiver blocks located on the
left side of the device as well.
Figure 2–4
device. The number of ITB clock lines available in any Stratix IV GT device is equal to
the number of refclk pins available in that device.
shows the input reference clock sources for CMU PLLs, ATX PLLs, and
also shows the ITB clock lines on the right side of the EP4S100G5F45
ITB[7:0]
8
refclk0
refclk0
refclk1
refclk0
refclk0
refclk1
6
6
refclk1
6
refclk1
6
2
2
2
2
2
2
2
2
PLL Cascade Clock
PLL Cascade Clock
Global Clock Line
Global Clock Line
Global Clock Line
PLL Cascade Clock
Global Clock Line
PLL Cascade Clock
Global Clock Line
PLL Cascade Clock
Global Clock Line
PLL Cascade Clock
ITB Clock Lines
ITB Clock Lines
ITB Clock Lines
Chapter 2: Transceiver Clocking in Stratix IV Devices
8
8
6
6
6
8
6
Transceiver Block GXBR3
Transceiver Block GXBR2
Transceiver Block GXBR1
Transceiver Block GXBR0
ATX PLL R2 (10G)
ATX PLL R1 (6G)
ATX PLL R0 (6G)
Two CMU PLLs
Two CMU PLLs
Two CMU PLLs
Two CMU PLLs
Four RX CDRs
Four RX CDRs
Four RX CDRs
Four RX CDRs
February 2011 Altera Corporation
and
and
and
and
Input Reference Clocking
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