EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 720

• Manufacturer Part Number: EP4SGX360FH29C3N
• Description: IC STRATIX IV FPGA 360K 780HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX360FH29C3N

• Number Of Logic Elements/cells: 353600
• Number Of Labs/clbs: 14144
• Total Ram Bits: 22564
• Number Of I /o: 289
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

2–48
Figure 2–27. Receiver Datapath Clocking in x8 Bonded Channel Configuration
Note to
(1) The red lines represent the FPGA fabric-Transceiver interface clock, the green lines represent the low-speed parallel clock, the dark red lines
Stratix IV Device Handbook Volume 2: Transceivers
represent the parallel recovered clock, and the blue lines represent the serial recovered clock.
Figure
rx_coreclk[7:4]
rx_coreclk[3:0]
FPGA
Fabric
2–27:
FPGA Fabric_Transceiver
Interface Clock
coreclkout
x8 Bonded Channel Configuration
PCIe ×8 functional mode supports the ×8 receiver channel bonding configuration. The
eight bonded channels are located in two transceiver blocks, referred to as the master
transceiver block and slave transceiver block, with four channels each.
Figure 2–27
configuration.
hard IP
hard IP
PCIe
PCIe
Interface
Interface
PIPE
PIPE
shows the receiver datapath clocking in PCIe ×8 bonded channel
Reference
Reference
Clock
Clock
Input
Input
Compensation
Compensation
RX Phase
RX Phase
FIFO
FIFO
/2
CMU0 PLL
CMU1 PLL
CMU1 PLL
CMU0 PLL
Ordering
Ordering
Byte
Byte
Serializer
Serializer
Byte
De-
/2
Byte
De-
/2
Slave Transceiver Block
Master Transceiver Block
Low-Speed Parallel Clock from CMU0 Clock Divider
CMU1 Clock
CMU0 Clock
CMU1 Clock
Low-Speed Parallel Clock from CMU0 Clock Divider
CMU0 Clock
Divider
Divider
Divider
Divider
Decoder
Decoder
8B/10B
8B/10B
CMU1 Channel
CMU0 Channel
CMU0 Channel
CMU1 Channel
Chapter 2: Transceiver Clocking in Stratix IV Devices
Receiver Channel PCS
Receiver Channel PCS
Match
Match
Rate
FIFO
Rate
FIFO
Parallel Recovered Clock
Parallel Recovered Clock
(Note 1)
Aligner
Aligner
Word
Word
Transceiver Channel Datapath Clocking
February 2011 Altera Corporation
Receiver Channel PMA
Serializer
Receiver Channel PMA
Serializer
De-
De-
CDR
CDR
Serial Recovered Clock
Serial Recovered Clock
Input Reference Clock
Input Reference Clock