EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 167

• Manufacturer Part Number: EP4SGX360FH29C3N
• Description: IC STRATIX IV FPGA 360K 780HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX360FH29C3N

• Number Of Logic Elements/cells: 353600
• Number Of Labs/clbs: 14144
• Total Ram Bits: 22564
• Number Of I /o: 289
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 5: Clock Networks and PLLs in Stratix IV Devices
PLLs in Stratix IV Devices
Table 5–16. Dynamic Phase-Shifting Control Signals (Part 2 of 2)
February 2011 Altera Corporation
SCANCLK
PHASEDONE
Signal Name
Table 5–17
PHASECOUNTERSELECT setting.
Table 5–17. Phase Counter Select Mapping
To perform one dynamic phase-shift, follow these steps:
1. Set PHASEUPDOWN and PHASECOUNTERSELECT as required.
2. Assert PHASESTEP. Each PHASESTEP pulse enables one phase shift. The PHASESTEP
3. Wait for PHASEDONE to go low.
4. De-assert PHASESTEP.
5. Wait for PHASEDONE to go high.
6. Repeat steps 1-5 as many times as required to perform multiple phase-shifts.
All signals are synchronous to SCANCLK and are latched on the SCANCLK edges and
must meet tsu/th requirements with respect to SCANCLK edges.
Free running clock from the core used
in combination with PHASESTEP to
enable and disable dynamic phase
shifting. Shared with SCANCLK for
dynamic reconfiguration.
When asserted, this indicates to
core-logic that the phase adjustment is
complete and the PLL is ready to act
on a possible second adjustment
pulse. Asserts based on internal PLL
timing. De-asserts on the rising edge
of SCANCLK.
pulses must be at least one scanclk cycle apart.
PHASECOUNTERSELECT[3]
lists the PLL counter selection based on the corresponding
Description
0
0
0
0
0
0
0
0
1
1
1
1
[2]
0
0
0
0
1
1
1
1
0
0
0
0
GCLK, RCLK or I/O pin
PLL reconfiguration
circuit
[1]
Source
0
0
1
1
0
0
1
1
0
0
1
1
[0]
0
1
0
1
0
1
0
1
0
1
0
1
PLL reconfiguration circuit
Logic array or I/O pins
Stratix IV Device Handbook Volume 1
All Output Counters
Destination
C0 Counter
C1 Counter
C2 Counter
C3 Counter
C4 Counter
C5 Counter
C6 Counter
C7 Counter
C8 Counter
C9 Counter
M Counter
Selects
5–51