EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 736
EP4SGX360FH29C3N
Manufacturer Part Number
EP4SGX360FH29C3N
Description
IC STRATIX IV FPGA 360K 780HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
Specifications of EP4SGX360FH29C3N
Number Of Logic Elements/cells
353600
Number Of Labs/clbs
14144
Total Ram Bits
22564
Number Of I /o
289
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Manufacturer:
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Stratix IV Device Handbook Volume 2: Transceivers
1
Non-Bonded Channel Configuration Without Rate Matcher
In non-bonded channel configuration without rate matcher, the Quartus II software
cannot determine if the incoming serial data in all channels have a 0 PPM frequency
difference. The Quartus II software automatically drives the read port of the receiver
phase compensation FIFO in each channel with the recovered clock driven on the
rx_clkout port of that channel. Use the rx_clkout signal from each channel to latch
its receiver data and status signals in the FPGA fabric.
This configuration uses one FPGA global, regional clock, or both, resource per
channel for the rx_clkout signal.
Chapter 2: Transceiver Clocking in Stratix IV Devices
FPGA Fabric-Transceiver Interface Clocking
February 2011 Altera Corporation
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