EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 46

• Manufacturer Part Number: EP4SGX360FH29C3N
• Description: IC STRATIX IV FPGA 360K 780HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX360FH29C3N

• Number Of Logic Elements/cells: 353600
• Number Of Labs/clbs: 14144
• Total Ram Bits: 22564
• Number Of I /o: 289
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

2–10
Figure 2–8. Input Function in Normal Mode
Notes to
(1) If you use datae1 and dataf1 as inputs to a six-input function, datae0 and dataf0 are available for register packing.
(2) The dataf1 input is available for register packing only if the six-input function is unregistered.
Stratix IV Device Handbook Volume 1
Figure
2–8:
These inputs are available for register packing.
For the packing of 2 five-input functions into one ALM, the functions must have at
least two common inputs. The common inputs are dataa and datab. The combination
of a four-input function with a five-input function requires one common input (either
dataa or datab).
In the case of implementing 2 six-input functions in one ALM, four inputs must be
shared and the combinational function must be the same. In a sparsely used device,
functions that could be placed in one ALM may be implemented in separate ALMs by
the Quartus II software to achieve the best possible performance. As a device begins
to fill up, the Quartus II software automatically uses the full potential of the Stratix IV
ALM. The Quartus II Compiler automatically searches for functions using common
inputs or completely independent functions to be placed in one ALM to make efficient
use of device resources. In addition, you can manually control resource usage by
setting location assignments.
You can implement any six-input function using inputs dataa, datab, datac, datad,
and either datae0 and dataf0 or datae1 and dataf1. If you use datae0 and dataf0, the
output is driven to register0, and/or register0 is bypassed and the data drives out
to the interconnect using the top set of output drivers (refer to
datae1 and dataf1, the output either drives to register1 or bypasses register1 and
drives to the interconnect using the bottom set of output drivers. The Quartus II
Compiler automatically selects the inputs to the LUT. ALMs in normal mode support
register packing.
datae0
datae1
dataf0
dataf1
dataa
datab
datac
datad
(2)
(Note 1)
6-Input
LUT
Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices
labclk
D
D
reg0
reg1
Q
Q
To general or
local routing
To general or
local routing
To general or
local routing
February 2011 Altera Corporation
Figure
Adaptive Logic Modules
2–8). If you use