EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 738
EP4SGX360FH29C3N
Manufacturer Part Number
EP4SGX360FH29C3N
Description
IC STRATIX IV FPGA 360K 780HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
Specifications of EP4SGX360FH29C3N
Number Of Logic Elements/cells
353600
Number Of Labs/clbs
14144
Total Ram Bits
22564
Number Of I /o
289
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4SGX360FH29C3N
Manufacturer:
Bussmann
Quantity:
40 000
Company:
Part Number:
EP4SGX360FH29C3N
Manufacturer:
ALTERA21
Quantity:
53
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SGX110DF29C3N PDF datasheet #6
- Current page: 738 of 1154
- Download datasheet (32Mb)
2–66
Figure 2–35. FPGA Fabric-Receiver Interface Clocking in a x4 Bonded Channel Configuration
Note to
(1) The green lines represent low-speed parallel clock from the CMU0 clock divider.
Stratix IV Device Handbook Volume 2: Transceivers
Figure
2–35:
1
Bonded Channel Configuration
All bonded transceiver channel configurations have rate matcher in the receiver data
path. In ×4 and ×8 bonded channel configurations, the Quartus II software
automatically drives the read port of the receiver phase compensation FIFO in all
channels with the coreclkout signal (from the master transceiver block in the case of
×8 bonded mode). Use the coreclkout signal to latch the receiver data and status
signals from all channels in the FPGA fabric.
This configuration uses one FPGA global and/or regional clock resource per bonded
link for the coreclkout signal.
Figure 2–35
configuration.
and Status
and Status
Channel 3
Channel 2
Channel 1
and Status
Channel 0
and Status
RX Data
RX Data
RX Data
RX Data
Logic
Logic
Logic
Logic
FPGA
Fabric
rx_coreclk[2]
rx_coreclk[1]
rx_coreclk[0]
rx_coreclk[3]
shows the FPGA fabric-Receiver interface clocking in ×4 bonded channel
coreclkout
Reference
Clock
/2
Compensation
Compensation
CMU1
CMU0
Compensation
Compensation
Compensation
rdclk
rdclk
rdclk
rdclk
rdclk
PLL
PLL
RX Phase
RX Phase
RX Phase
RX Phase
RX Phase
FIFO
FIFO
FIFO
FIFO
FIFO
wrclk
wrclk
wrclk
wrclk
wrclk
Divider
CMU0
Clock
/2
/2
/2
/2
Chapter 2: Transceiver Clocking in Stratix IV Devices
Low-Speed Parallel Clock
from CMU0 Clock Divider
Low-Speed Parallel Clock
from CMU0 Clock Divider
Low-Speed Parallel Clock
from CMU0 Clock Divider
Low-Speed Parallel Clock
from CMU0 Clock Divider
Transmitter Channel PCS
Transmitter Channel PCS
Transmitter Channel PCS
Transmitter Channel PCS
CMU1 Channel
CMU0 Channel
Channel 2
Channel 3
Channel 1
FPGA Fabric-Transceiver Interface Clocking
Channel 0
February 2011 Altera Corporation
(Note 1)
Related parts for EP4SGX360FH29C3N
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Classic EPLD
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 25 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: