EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 808
EP4SGX360FH29C3N
Manufacturer Part Number
EP4SGX360FH29C3N
Description
IC STRATIX IV FPGA 360K 780HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
Specifications of EP4SGX360FH29C3N
Number Of Logic Elements/cells
353600
Number Of Labs/clbs
14144
Total Ram Bits
22564
Number Of I /o
289
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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4–2
User Reset and Power-Down Signals
Table 4–1. Transceiver Channel Reset Signals
Stratix IV Device Handbook Volume 2: Transceivers
tx_digitalreset
rx_digitalreset
rx_analogreset
Note to
(1) Assert this signal until the clocks coming out of the transmitter PLL and receiver CDR are stabilized. Stable parallel clocks are essential for
proper operation of the transmitter and receiver phase-compensation FIFOs in the PCS.
Table
4–1:
Signal
1
(1)
(1)
Each transceiver channel in the Stratix IV device has individual reset signals to reset
its physical coding sublayer (PCS) and physical medium attachment (PMA) blocks.
Each CMU PLL in the transceiver block has a dedicated reset signal. The transceiver
block also has a power-down signal that affects all the channels and CMU PLLs in the
transceiver block.
All reset and power-down signals are asynchronous.
Table 4–1
lists the reset signals available for each transceiver channel.
■
■
■
■
■
■
Transmitter Only
Receiver and Transmitter
Receiver Only
Receiver and Transmitter
Receiver Only
Receiver and Transmitter
ALTGX MegaWizard Plug-In
Manager Configurations
Chapter 4: Reset Control and Power Down in Stratix IV Devices
Provides asynchronous reset to all digital logic in
the transmitter PCS, including the XAUI transmit
state machine.
The minimum pulse width for this signal is two
parallel clock cycles.
Resets all digital logic in the receiver PCS,
including:
■
■
■
■
■
The minimum pulse width for this signal is two
parallel clock cycles.
Resets the receiver CDR present in the receiver
channel.
The minimum pulse width is two parallel clock
cycles.
XAUI receiver state machines
GIGE receiver state machines
XAUI channel alignment state machine
BIST-PRBS verifier
BIST-incremental verifier
Description
User Reset and Power-Down Signals
February 2011 Altera Corporation
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