EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 993

• Manufacturer Part Number: EP4SGX360FH29C3N
• Description: IC STRATIX IV FPGA 360K 780HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX360FH29C3N

• Number Of Logic Elements/cells: 353600
• Number Of Labs/clbs: 14144
• Total Ram Bits: 22564
• Number Of I /o: 289
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Protocol Settings
Figure 1–12. MegaWizard Plug-In Manager—ALTGX (8B10B Screen)
Table 1–11. MegaWizard Plug-In Manager Options (8B10B Screen) (Part 1 of 3)
February 2011 Altera Corporation
Enable low latency PCS mode.
Enable 8B/10B
decoder/encoder.
Create a tx_forcedisp to
enable Force disparity and use
tx_dispval to code up the
incoming word using positive
or negative disparity.
ALTGX Setting
8B10B Screen for the Protocol Settings
Figure 1–12
Protocol Settings.
Table 1–11
Manager for your ALTGX custom megafunction variation.
This option disables all the PCS blocks except the
Transmitter/Receiver Phase Comp FIFO and optional
byte serializer/de-serializer.
This option is available if the channel width is 8-bits,
16-bits, or 32-bits.
8B/10B encoder force disparity control:
■
■
When asserted high—forces the 8B/10B encoder to
encode the data on the tx_datain port with a
positive or negative disparity depending on the
tx_dispval signal level.
When de-asserted low—the 8B/10B encoder
encodes the data on the tx_datain port according
to the 8B/10B running disparity rules.
lists the available options on the 8B10B screen of the MegaWizard Plug-In
shows the 8B10B screen of the MegaWizard Plug-In Manager for the
Description
“Low Latency PCS Datapath”
section in the
Architecture in Stratix IV Devices
chapter.
“8B/10B Decoder” section in the
Transceiver Architecture in
Stratix IV Devices
“8B/10B Encoder” and
“Transceiver Port Lists” sections
in the
Stratix IV Devices
Stratix IV Device Handbook Volume 3
Transceiver Architecture in
Reference
Transceiver
chapter.
chapter.
1–35