EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 466

• Manufacturer Part Number: EP4SGX360FH29C3N
• Description: IC STRATIX IV FPGA 360K 780HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX360FH29C3N

• Number Of Logic Elements/cells: 353600
• Number Of Labs/clbs: 14144
• Total Ram Bits: 22564
• Number Of I /o: 289
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

1–22
Stratix IV Device Handbook Volume 2: Transceivers
The byte serializer forwards the LSByte first, followed by the MSByte. The input data
width to the byte serializer depends on the channel width option that you selected in
the ALTGX MegaWizard Plug-In Manager. For example, in single-width mode,
assuming a channel width of 20, the byte serializer sends out the least significant
word datain[9:0] of the parallel data from the FPGA fabric, followed by
datain[19:10].
in single-width mode.
Table 1–9. Input and Output Data Width of the Byte Serializer in Single-Width Mode
Figure 1–16
width, refer to
Figure 1–16. Byte Serializer Datapath in Double-Width Mode
Notes to
(1) For the datain[] and dataout[] port width, refer to
(2) The datain signal is the input from the FPGA fabric that has already passed through the TX phase compensation
The operation in double-width mode is similar to that of single-width mode. For
example, assuming a channel width of 40, the byte serializer forwards datain[19:0]
first, followed by datain[39:20].
the byte serializer in double-width mode.
Table 1–10. Input and Output Data Width of the Byte Serializer in Double-Width Mode
Asserting the tx_digitalreset signal resets the byte serializer block.
If you select the 8B/10B Encoder option in the ALTGX MegaWizard Plug-In Manager,
the 8B/10B encoder uses the output from the byte serializer. Otherwise, the byte
serializer output is forwarded to the serializer.
Single-width mode
Double-width mode
FIFO.
Double-Width Mode
Deserialization Width
Deserialization Width
Figure
shows the byte serializer datapath in double-width mode. For data port
1–16:
Table
Table 1–9
1–10.
lists the input and output data widths of the byte serializer
datain[]
Input Data Width to the Byte
Input Data Width to the Byte
Table 1–10
Byte Serializer
Serializer
Serializer
Chapter 1: Transceiver Architecture in Stratix IV Devices
32
40
/2
16
20
lists the input and output data widths of
Table
1–10.
Low-Speed Parallel
dataout[]
Clock
(Note
Output Data Width from the
1),
Output Data Width from the
February 2011 Altera Corporation
(2)
Transceiver Block Architecture
Byte Serializer
Byte Serializer
16
20
10
8