EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 521
EP4SGX360FH29C3N
Manufacturer Part Number
EP4SGX360FH29C3N
Description
IC STRATIX IV FPGA 360K 780HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
Specifications of EP4SGX360FH29C3N
Number Of Logic Elements/cells
353600
Number Of Labs/clbs
14144
Total Ram Bits
22564
Number Of I /o
289
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Figure 1–59. Deskew FIFO Operation in XAUI Functional Mode
Note to
(1) This figure is from IEEE P802.3ae.
February 2011 Altera Corporation
Figure
1–59:
The deskew operation in XAUI functional mode is compliant to the PCS deskew state
machine diagram specified in clause 48 of IEEE P802.3ae, as shown in
Rate Match (Clock Rate Compensation) FIFO
In asynchronous systems, the upstream transmitter and local receiver can be clocked
with independent reference clocks. Frequency differences in the order of a few
hundred PPM can corrupt the data when latching from the recovered clock domain
(the same clock domain as the upstream transmitter reference clock) to the local
receiver reference clock domain.
The rate match FIFO compensates for small clock frequency differences between the
upstream transmitter and the local receiver clocks by inserting or removing SKP
symbols or ordered sets from the IPG or idle streams. It deletes SKP symbols or
ordered sets when the upstream transmitter reference clock frequency is higher than
the local receiver reference clock frequency. It inserts SKP symbols or ordered-sets
when the local receiver reference clock frequency is higher than the upstream
transmitter reference clock frequency.
deskew_error * SUDI
deskew_error * SUDI
deskew_error * SUDI
deskew_error * SUDI
deskew_error * SUDI
deskew_error * SUDI
deskew_error * SUDI
SUDI(![/||A||/])
enable_deskew
enable_deskew
AUDI
AUDI
AUDI
AUDI
AUDI
AUDI
AUDI
AUDI
LOSS_OF_ALIGNMENT
enable_deskew
1
2
3
ALIGN_ACQUIRED_1
ALIGN_ACQUIRED_2
ALIGN_ACQUIRED_3
ALIGN_ACQUIRED_4
align_status
ALIGN_DETECT_1
ALIGN_DETECT_2
ALIGN_DETECT_3
(Note 1)
SUDI(![/||A||/])
SUDI(![/||A||/])
SUDI(![/||A||/])
SUDI(![/||A||/])
sync_status OK * SUDI(![/||A||/])
⇐
⇐
⇐
⇐
FAIL
FALSE
FALSE
TRUE
1
2
3
SUDI(![/||A||/])
SUDI(![/||A||/])
SUDI(![/||A||/])
reset +
(sync_status=FAIL * SUDI)
Stratix IV Device Handbook Volume 2: Transceivers
!deskew_error
* SUDI(![/||A||/])
!deskew_error
* SUDI(![/||A||/])
!deskew_error
* SUDI(![/||A||/])
!deskew_error
* SUDI(![/||A||/])
!deskew_error
* SUDI(![/||A||/])
!deskew_error
* SUDI(![/||A||/])
!deskew_error
* SUDI(![/||A||/])
Figure
1–59.
1–77
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