EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 93

• Manufacturer Part Number: EP4SGX360FH29C3N
• Description: IC STRATIX IV FPGA 360K 780HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX360FH29C3N

• Number Of Logic Elements/cells: 353600
• Number Of Labs/clbs: 14144
• Total Ram Bits: 22564
• Number Of I /o: 289
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 4: DSP Blocks in Stratix IV Devices
Stratix IV DSP Block Resource Descriptions
February 2011 Altera Corporation
Pipeline Register Stage
Second-Stage Adder
1
1
1
Each half block has its own signa and signb signal. Therefore, all of the data A inputs
feeding the same half DSP block must have the same sign representation. Similarly, all
of the data B inputs feeding the same half DSP block must have the same sign
representation. The multiplier offers full precision regardless of the sign
representation in all operational modes except for full precision 18 × 18 loopback and
two-multiplier adder modes. For more information, refer to
Sum Mode” on page
By default, when the signa and signb signals are unused, the Quartus II software sets
the multiplier to perform unsigned multiplication.
Figure 4–6 on page 4–9
that can feed into the first-stage adder. There are four first-stage adders in a DSP block
(two adders per half DSP block). The first-stage adder block has the ability to perform
addition and subtraction. The control signal for addition or subtraction is static and
has to be configured after compile time. The first-stage adders are used by the sum
modes to compute the sum of two multipliers, 18 × 18-complex multipliers, and to
perform the first stage of a 36 × 36 multiply and shift operations.
Depending on your specifications, the output of the first-stage adder has the option to
feed into the pipeline registers, second-stage adder, rounding and saturation unit, or
output registers.
Figure 4–6 on page 4–9
feed or bypass the pipeline registers. Pipeline registers increase the DSP block’s
maximum performance (at the expense of extra cycles of latency), especially when
using the subsequent DSP block stages. Pipeline registers split up the long signal path
between the input registers/multiplier/first-stage adder and the second-stage adder/
round-and-saturation/output registers, creating two shorter paths.
There are four individual 44-bit second-stage adders per DSP block (two adders
per half DSP block). You can configure the second-stage adders as follows:
■
■
■
■
You can use the chained-output adder at the same time as a second-level adder in
chained output summation mode.
The output of the second-stage adder has the option to go into the rounding and
saturation logic unit or the output register.
You cannot use the second-stage adder independently from the multiplier and
first-stage adder.
The final stage of a 36-bit multiplier
A sum of four (18 × 18)
An accumulator (44-bits maximum)
A chained output summation (44-bits maximum)
4–22.
shows that the outputs of the multipliers are the only outputs
shows that the output from the first-stage adder can either
Stratix IV Device Handbook Volume 1
“Two-Multiplier Adder
4–13