EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 552

• Manufacturer Part Number: EP4SGX360FH29C3N
• Description: IC STRATIX IV FPGA 360K 780HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX360FH29C3N

• Number Of Logic Elements/cells: 353600
• Number Of Labs/clbs: 14144
• Total Ram Bits: 22564
• Number Of I /o: 289
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

1–108
Table 1–39. Transmit and Receive Serial Pins (Part 2 of 2)
Stratix IV Device Handbook Volume 2: Transceivers
GXB_TX_[L,R][1,3,5,7]P
Notes to
(1) These indexes are for the Stratix IV GX and GT device with the maximum number of transceiver blocks. For exact information about how many
(2) Pins 0,2,4,6 are hardwired to CMU channel0 in the corresponding transceiver blocks.
(3) Pins 1,3,5,7 are hardwired to CMU channel1 in the corresponding transceiver blocks.
of these pins are available for a specific device family, refer to the
Table
1–39:
f
1
Pins
Interpret the pins column as follows:
The receiver serial input pins are hardwired to their corresponding CMU channels.
For more information, refer to the notes to
Serializer and Deserializer
The serializer and deserializer convert the serial-to-parallel data on the transmitter
and receiver side, respectively. The ALTGX MegaWizard Plug-In Manager provides
the Basic (PMA Direct) functional mode (with a none and ×N option) to configure a
transceiver channel to enable the transmitter serializer and receiver deserializer. To
configure a CMU channel as a transceiver channel, you must use this functional
mode.
The input data width options to serializer/from deserializer for a channel configured
in this mode are 8, 10, 16, and 20.
To understand the maximum FPGA fabric-transceiver interface clock frequency
limits, refer to the “Transmitter Channel Datapath Clocking” section in the
Clocking in Stratix IV Devices
CMU Clock Divider
When you configure a CMU channel in Basic (PMA Direct) ×1 mode, the CMU clock
divider divides the high-speed clock from the other CMU channel (used as a clock
generation unit) within the same transceiver block and provides the high-speed serial
clock and low-speed parallel clocks to the transmitter side of the CMU channel. The
CMU clock divider can divide the high-speed clock by /1, /2, and /4.
(1)
(3)
For pins REFCLK_[L,R][0,2,4,6]P and GXB_CMURX_[L_R][0,2,4,6], the “L, R”
indicates the left and right side and the “0, 2, 4, 6” indicates the different pins.
For example, a pin on the left side with index 0 is named: REFCLK_L0P,
GXB_CMURX_L0P.
When a CMU Channel is Configured
Transmit serial output for CMU
chapter.
as a Transceiver Channel
Stratix IV Device Family Overview
Channel1
Table
Chapter 1: Transceiver Architecture in Stratix IV Devices
1–39.
chapter.
February 2011 Altera Corporation
When a CMU Channel is
Configured for Clock
Not available for use
Transceiver Block Architecture
Generation
Transceiver