EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 661

• Manufacturer Part Number: EP4SGX360FH29C3N
• Description: IC STRATIX IV FPGA 360K 780HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX360FH29C3N

• Number Of Logic Elements/cells: 353600
• Number Of Labs/clbs: 14144
• Total Ram Bits: 22564
• Number Of I /o: 289
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Port Lists
Table 1–74. Stratix IV GX and GT ALTGX Megafunction Ports: Receiver Ports (Part 6 of 7)
February 2011 Altera Corporation
rx_coreclk
rx_phase_comp_fifo_
error
Receiver Physical Media Attachment (PMA)
rx_datain
rx_cruclk
rx_pll_locked
rx_freqlocked
rx_locktodata
Port Name
Output
Output
Output
Output
Input/
Input
Input
Input
Input
coreclkout for
Synchronous to
bonded modes.
tx_clkout for
tx_clkout or
Asynchronous
Asynchronous
Asynchronous
Clock Domain
coreclkout.
Clock signal
non-bonded
Clock signal
modes.
signal
signal
signal
N/A
Optional read clock port for the receiver phase
compensation FIFO.
■
■
Receiver phase compensation FIFO full or
empty indicator.
■
Receiver serial data input port.
Input reference clock for the receiver clock and
data recovery.
Receiver CDR lock-to-reference indicator.
■
■
Receiver CDR lock mode indicator.
■
■
Receiver CDR lock-to-data mode control signal.
■
■
If not selected—the Quartus II software
automatically selects
rx_clkout/tx_clkout/
coreclkout as the read clock for the
receiver phase compensation FIFO.
If selected—drive this port with a clock that
has 0 PPM difference with respect to
rx_clkout/tx_clkout/
coreclkout.
A high level—the receiver phase
compensation FIFO is either full or empty.
A high level—the receiver CDR is locked to
the input reference clock.
A low level—the receiver CDR is not locked
to the input reference clock.
A high level—the receiver CDR is in
lock-to-data mode.
A low level—the receiver CDR is in
lock-to-reference mode.
When asserted high—the receiver CDR is
forced to lock-to-data mode.
When de-asserted low—the receiver CDR
lock mode depends on the
rx_locktorefclk signal level.
Stratix IV Device Handbook Volume 2: Transceivers
Description
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Scope
1–217