EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 587

• Manufacturer Part Number: EP4SGX360FH29C3N
• Description: IC STRATIX IV FPGA 360K 780HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX360FH29C3N

• Number Of Logic Elements/cells: 353600
• Number Of Labs/clbs: 14144
• Total Ram Bits: 22564
• Number Of I /o: 289
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Table 1–53. PCIe Rateswitch Controller and Clock Switch Circuitry
February 2011 Altera Corporation
Channel
Bonding
Option
×1
×4
×8
Individual channel PCS block
CMU0_Channel
CMU0_Channel of the master
transceiver block
Location of PCIe Rateswitch
Controller Module
PCIe transmitter high-speed serial and low-speed parallel clock switch occurs:
■
■
■
In PCIe ×1, ×4, and ×8 modes, the recovered clock switch happens in the receiver CDR
of each transceiver channel.
Table 1–53
switch circuitry in PCIe ×1, ×4, and ×8 modes.
In PCIe ×1 mode, the CMU_PLL clock switch occurs in the local clock divider in each
transceiver channel.
In PCIe ×4 mode, the CMU_PLL clock switch occurs in the CMU0 clock divider in the
CMU0_Channel within the transceiver block.
In PCIe ×8 mode, the CMU_PLL clock switch occurs in the CMU0 clock divider in the
CMU0_Channel within the master transceiver block.
lists the locations of the PCIe rateswitch controller and the PCIe clock
Local clock divider in transmitter PMA
of each channel
CMU0 clock divider in CMU0_Channel
CMU0 clock divider in CMU0_Channel
of the master transceiver block
Transmitter High-Speed Serial and
Low-Speed Parallel Clock Switch
Circuitry
Location of PCIe Clock Switch Circuitry
Stratix IV Device Handbook Volume 2: Transceivers
Recovered Clock Switch Circuitry
CDR block in receiver PMA of each
channel
CDR block in receiver PMA of each
channel
CDR block in receiver PMA of each
channel
1–143