EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 354

• Manufacturer Part Number: EP4SGX360FH29C3N
• Description: IC STRATIX IV FPGA 360K 780HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX360FH29C3N

• Number Of Logic Elements/cells: 353600
• Number Of Labs/clbs: 14144
• Total Ram Bits: 22564
• Number Of I /o: 289
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

10–20
Figure 10–7. Multi-Device Fast AS Configuration
Notes to
(1) Connect the pull-up resistors to V
(2) Connect the repeater buffers between the Stratix IV master and slave device(s) for
Stratix IV Device Handbook Volume 1
integrity and clock skew problems.
Serial Configuration
Figure
Device
10–7:
1
DATA
DCLK
ASDI
nCS
V
CCPGM (1)
Figure 10–7
As shown in
connected together with external pull-up resistors. These pins are open-drain
bidirectional pins on the devices. When the first device asserts nCEO (after receiving all
of its configuration data), it releases its CONF_DONE pin. But the subsequent devices in
the chain keep this shared CONF_DONE line low until they have received their
configuration data. When all target devices in the chain have received their
configuration data and have released CONF_DONE, the pull-up resistor drives a high
level on this line and all devices simultaneously enter initialization mode.
If an error occurs at any point during configuration, the nSTATUS line is driven low by
the failing device. If you enable the Auto-restart configuration after error option,
reconfiguration of the entire chain begins after a reset time-out period (a maximum of
500 μs). If you did not enable the Auto-restart configuration after error option, the
external system must monitor nSTATUS for errors and then pulse nCONFIG low to
restart configuration. The external system can pulse nCONFIG if it is under system
control rather than tied to V
If you have enabled the Auto-restart configuration after error option, the nSTATUS pin
transitions from high to low and back again to high when a configuration error is
detected. This appears as a low pulse at the nSTATUS pin with a minimum pulse width
of 10 μs to a maximum pulse width of 500 μs, as defined in the t
10
kΩ
Buffers (2)
CCPGM
V
CCPGM (1)
at a 3.0-V supply.
shows the pin connections for the multi-device fast AS configuration.
10
Figure
kΩ
Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices
V
GND
CCPGM (1)
10
10–7, the nSTATUS and CONF_DONE pins on all target devices are
kΩ
Stratix IV Device Master
nSTATUS
CONF_DONE
nCONFIG
nCE
DATA0
DCLK
nCSO
ASDO
CCGPM
MSEL2
MSEL1
MSEL0
.
nCEO
V
CCPGM
Fast Active Serial Configuration (Serial Configuration Devices)
DATA[0]
GND
and
DCLK
nSTATUS
CONF_DONE
nCONFIG
nCE
DATA0
DCLK
Stratix IV Device Slave
. This is to prevent potential signal
STATUS
April 2011 Altera Corporation
MSEL2
MSEL1
MSEL0
nCEO
specification.
GND
V
N.C.
CCPGM