EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 888

• Manufacturer Part Number: EP4SGX360FH29C3N
• Description: IC STRATIX IV FPGA 360K 780HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX360FH29C3N

• Number Of Logic Elements/cells: 353600
• Number Of Labs/clbs: 14144
• Total Ram Bits: 22564
• Number Of I /o: 289
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

5–42
Table 5–10. rx_dataoutfull[63:0] FPGA Fabric-Transceiver Channel Interface Signal Descriptions (Part 3 of 6)
Stratix IV Device Handbook Volume 2: Transceivers
16-bit FPGA fabric-transceiver
Channel Interface with PCS-PMA
set to 8/10 bits
16-bit FPGA fabric-transceiver
Channel Interface with PCS-PMA
set to 8/10 bits (continued)
Channel Interface Description
FPGA Fabric-Transceiver
Two 8-bit Data
rx_dataoutfull[7:0] - rx_dataout (LSByte) and rx_dataoutfull[39:32] -
rx_dataout (MSByte)
The following signals are used in 16-bit 8B/10B mode:
Two Control Bits
rx_dataoutfull[8] - rx_ctrldetect (LSB) and rx_dataoutfull[40] -
rx_ctrldetect (MSB)
Two Receiver Error Detect Bits
rx_dataoutfull[9] - rx_errdetect (LSB) and rx_dataoutfull[41]-
rx_errdetect (MSB)
Two Receiver Sync Status Bits
rx_dataoutfull[10] - rx_syncstatus (LSB) and rx_dataoutfull[42]-
rx_syncstatus (MSB)
Two Receiver Disparity Error Bits
rx_dataoutfull[11] - rx_disperr (LSB) and rx_dataoutfull[43] -
rx_disperr (MSB)
Two Receiver Pattern Detect Bits
rx_dataoutfull[12] - rx_patterndetect (LSB) and rx_dataoutfull[44] -
rx_patterndetect (MSB)
rx_dataoutfull[13] and rx_dataoutfull[45]: Rate Match FIFO deletion status
indicator (rx_rmfifodatadeleted) in non-PCIe/PCIe modes
rx_dataoutfull[14] and rx_dataoutfull[46]: Rate Match FIFO insertion status
indicator (rx_rmfifodatainserted) in non-PCIe/PCIe modes
Two 2-bit PCIe Status Bits
rx_dataoutfull[14:13] - rx_pipestatus (LSB) and rx_dataoutfull[46:45]-
rx_pipestatus (MSB)
rx_dataoutfull[15] and rx_dataoutfull[47]: 8B/10B running disparity indicator
(rx_runningdisp)
The following signals are used in 16-bit SONET/SDH mode:
Two 8-bit Data
rx_dataoutfull[7:0] - rx_dataout (LSByte) and rx_dataoutfull[39:32] -
rx_dataout (MSByte)
Two Receiver Alignment Pattern Length Bits
rx_dataoutfull[8] - rx_a1a2sizeout (LSB) and rx_dataoutfull[40]-
rx_a1a2sizeout (MSB)
Two Receiver Sync Status Bits
rx_dataoutfull[10] - rx_syncstatus (LSB) and rx_dataoutfull[42] -
rx_syncstatus (MSB)
Two Receiver Pattern Detect Bits
rx_dataoutfull[12] - rx_patterndetect (LSB) and rx_dataoutfull[44] -
rx_patterndetect (MSB)
Receive Signal Description (Based on Stratix IV GX Supported FPGA
Fabric-Transceiver Channel Interface Widths)
Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Modes Implementation
February 2011 Altera Corporation